| 1. A parallel conversion circuit that samples serial data with each symbol formed for each consecutive N bits therein, where
N is a natural number equal to or more than two, responsive to a first clock signal synchronized with the serial data, converts
the symbol to parallel signals based on a synchronization pattern timing signal, and retimes the parallel signals responsive
to a second clock signal, to output the retimed parallel signals as parallel data,
the synchronization pattern timing signal being synchronized with a timing of input of a first bit of the symbol constituting
the serial data,
said parallel conversion circuit comprising a circuit that obtains a phase difference between the synchronization pattern
timing signal and the second clock signal and outputs delay time information corresponding to said phase difference.
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