| US 7,594,207 B2 | ||
| Computationally efficient design rule checking for circuit interconnect routing design | ||
| Stefanus Mantik, San Jose, Calif. (US); Limin He, Saratoga, Calif. (US); Soohong Kim, Pleasanton, Calif. (US); Jimmy Lam, Cupertino, Calif. (US); and Jianmin Li, Cupertino, Calif. (US) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Sep. 13, 2006, as Appl. No. 11/521,270. | ||
| Prior Publication US 2008/0066027 A1, Mar. 13, 2008 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—4 [716/5; 716/12] | 28 Claims |
| 1. A computer-implemented method, comprising:
identifying, by a computer, an instance of a particular element-point pair, wherein the particular element-point pair indicates
an association between an interconnect element of a first type of interconnect element and a point located at a particular
spatial location relative to the interconnect element, and wherein the instance of the particular element-point pair is a
particular occurrence of the particular element-point pair involving a first interconnect element of the first type of interconnect
element and a first location in a circuit assembly design;
accessing previously computed marking information corresponding to the particular element-point pair, wherein the previously
computed marking information comprises information indicating one or more types of interconnect elements that can be positioned
at the particular spatial location without violating a set of one or more design rules applicable to the first type of interconnect
element; and
associating in machine memory the previously computed marking information with the instance of the particular element-point
pair such that the previously computed marking information is associated with the first location in the circuit assembly design
without having to recompute the previously computed marking information.
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