| US 7,594,201 B2 | ||
| Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code | ||
| Juergen Lahner, Morgan Hill, Calif. (US); Kiran Atmakuri, Sunnyvale, Calif. (US); and Kavitha Chaturvedula, San Jose, Calif. (US) | ||
| Assigned to LSI Corporation, Milpitas, Calif. (US) | ||
| Filed on Jul. 28, 2006, as Appl. No. 11/460,680. | ||
| Application 11/460680 is a continuation in part of application No. 10/844664, filed on May 12, 2004, granted, now 7,086,015. | ||
| Prior Publication US 2006/0282801 A1, Dec. 14, 2006 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—2 [716/3; 716/7; 716/13] | 28 Claims |
| 1. A method of optimizing register transfer level code for an integrated circuit design by a computer system comprising steps
of:
(a) receiving as input of the computer system a first register transfer level code for the integrated circuit design;
(b) receiving as input criteria defining a critical multiplex structure;
(c) analyzing the first register transfer level code to identify multiplex structures in the first register transfer level
code;
(d) comparing each of the multiplex structures identified in the first register transfer level code to the criteria defining
a critical multiplex structure;
(e) including each of the multiplex structures identified in the first register transfer level code that satisfy the criteria
defining a critical multiplex structure in a list of critical multiplex structures; and
(f) generating as output the list of critical multiplex structures.
|