a plurality of memory devices;

a memory bus coupled to the plurality of memory devices; and

a memory hub coupled to the plurality of memory devices through the memory bus, the memory hub comprising:

a link interface adapted to receive memory requests for access to memory locations in at least one memory device of the plurality of memory devices;

a memory device interface adapted to receive read data in response to memory requests;

a memory controller coupled to the link interface and the memory device interface, the memory controller operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface and further operable to adjust timing parameters responsive to a pointer offset signal indicative of a pointer offset; and

a synchronization module coupled to a memory device, the memory device interface and the memory controller, the memory device operating according to a first clock signal, the synchronization module operable to couple read data from the memory device to the memory controller, the memory controller operable to receive memory requests from the link interface responsive to a second clock signal, the synchronization module comprising:

a first pointer circuit, the first pointer circuit operable to generate a first pointer signal indicative of a data location in a buffer where data is to be stored in responsive to the first clock signal;

a second pointer circuit, the second pointer circuit operable to generate a second pointer signal indicative of a data location in the buffer where data is to be retrieved from responsive to the second clock signal; and

a comparison circuit coupled to the first pointer circuit and the second pointer circuit, the comparison circuit operable to compare the first pointer signal and the second pointer signal to generate the pointer offset signal.