| US 7,594,058 B2 | ||
| Chipset supporting a peripheral component interconnection express (PCI-E) architecture | ||
| Peter Chia, Hsin Tien (Taiwan); Chad Tsai, Hsin Tien (Taiwan); Jiin Lai, Hsin Tien (Taiwan); Edward Su, Hsin Tien (Taiwan); and Chih-Kuo Kao, Hsin Tien (Taiwan) | ||
| Assigned to Via Technologies, Inc., Taipei Hsien (Taiwan) | ||
| Filed on Nov. 07, 2005, as Appl. No. 11/267,498. | ||
| Prior Publication US 2007/0106826 A1, May 10, 2007 | ||
| Int. Cl. G06F 13/36 (2006.01) | ||
| U.S. Cl. 710—309 [710/242; 710/306] | 10 Claims |
| 4. A chipset supporting a peripheral component interconnection Express (PCI-E) architecture, wherein the chipset is connected
among a microprocessor, a plurality of first PCI-E ports and a plurality of second PCI-E ports, the chipset comprising:
a first port arbiter, receiving data and arbitrating data priority from said first PCI-E ports;
a second port arbiter, receiving data and arbitrating data priority from said second PCI-E ports;
a first URD (upstream range decoding) logic, decoding the data from said first port arbiter;
a second URD (upstream range decoding) logic, decoding the data from said second port arbiter;
an upstream arbiter, receiving the data and arbitrating data priority from said first URD logic and said second URD logic;
a downstream arbiter, receiving the data and arbitrating data priority from said microprocessor, said first URD logic and
said second URD logic;
a DARD (downstream address range decoding) logic, decoding the data from said downstream arbiter and dispatching the data
to a corresponding second PCI-E port chosen from said second PCI-E ports if the data come from one of said second PCI-E ports;
and
a device arbiter, receiving the data and arbitrating data priority from said first URD logic and said DARD logic and transmit
the data to a corresponding first PCI-E port chosen from said first PCI-E ports;
wherein said first URD logic dispatching data to said microprocessor if the data hit an on board range table, to said device
arbiter if the data hit an PCI-E device range table, or to said downstream arbiter if the data hit neither said PCI-E device
range table nor said onboard range table; and
wherein said second URD logic dispatching data to said upstream arbiter if the data hit an on board range table, otherwise,
to said downstream arbiter.
|