| US 7,592,685 B2 | ||
| Device and methodology for reducing effective dielectric constant in semiconductor devices | ||
| Daniel C. Edelstein, White Plains, N.Y. (US); Matthew E. Colburn, Hopewell Junction, N.Y. (US); Edward C. Cooney, III, Jericho, Vt. (US); Timothy J. Dalton, Ridgefield, Conn. (US); John A. Fitzsimmons, Poughkeepsie, N.Y. (US); Jeffrey P. Gambino, Westford, Vt. (US); Elbert E. Huang, Tarrytown, N.Y. (US); Michael W. Lane, Cortlandt Manor, N.Y. (US); Vincent J. McGahay, Poughkeepsie, N.Y. (US); Lee M. Nicholson, Katonah, N.Y. (US); Satyanarayana V. Nitta, Poughquag, N.Y. (US); Sampath Purushothaman, Yorktown Heights, N.Y. (US); Sujatha Sankaran, Wappingers Falls, N.Y. (US); Thomas M. Shaw, Peekskill, N.Y. (US); Andrew H. Simon, Fishkill, N.Y. (US); and Anthony K. Stamper, Williston, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Aug. 31, 2007, as Appl. No. 11/849,048. | ||
| Application 11/849048 is a division of application No. 10/707996, filed on Jan. 30, 2004, granted, now 7,405,147. | ||
| Prior Publication US 2008/0038915 A1, Feb. 14, 2008 | ||
| Int. Cl. H01L 29/93 (2006.01) | ||
| U.S. Cl. 257—522 [257/499] | 20 Claims |
| 1. A semiconductor structure, comprising:
an insulator layer having interconnect features;
at least one gap formed in the insulator layer spanning more than a minimum spacing of the interconnect features; and
the at least one gap including an undercut beneath each of two adjacent interconnect features,
wherein a top surface of the insulator layer is arranged on a same plane as a top surface of the interconnect features.
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