| US 7,592,673 B2 | ||
| ESD protection circuit with isolated diode element and method thereof | ||
| David C. Burdeaux, Phoenix, Ariz. (US); and Daniel J. Lamey, Phoenix, Ariz. (US) | ||
| Assigned to Freescale Semiconductor, Inc., Austin, Tex. (US) | ||
| Filed on Mar. 28, 2007, as Appl. No. 11/692,722. | ||
| Prior Publication US 2007/0228475 A1, Oct. 04, 2007 | ||
| Int. Cl. H01L 23/62 (2006.01) | ||
| U.S. Cl. 257—355 [257/E27.112; 438/237; 361/111] | 14 Claims |

| 1. An ESD protection circuit comprising:
an ESD device, wherein the ESD device includes a source, a gate and a drain;
a junction isolation diode coupled between the drain of the ESD device and a ground potential for providing junction isolation
of the drain; and
an isolation diode element coupled in series with the ESD device and configured for providing ESD protection to a transistor
device needing ESD protection having a source, a gate and a drain, wherein (i) responsive to −Vgs conditions on a gate of
the protected transistor device, the series coupled isolation diode element prevents a forward biasing of the drain-source
junction of the ESD transistor prior to a breakdown condition of the isolation diode element, (ii) responsive to an ESD event
sufficient to cause damage to the transistor device needing ESD protection, the series coupled isolation diode element permits
an occurrence of the breakdown condition, further wherein the ESD protection circuit can operate in both (i) a polarity of
normal operation of the protected device and (ii) an opposite polarity other than in normal operation of the transistor device
needing ESD protection; and (iii) the source of the transistor device needing ESD protection is connected to the source of
the ESD device by a back side of a substrate of the ESD protection circuit, the substrate comprising an SOI substrate and
an isolation region that is bounded by (i) trench isolation and (ii) an insulator layer of the SOI substrate, the isolation
diode element comprising a diode element isolated from the substrate by the isolation region in the substrate between the
ESD device and the transistor device needing ESD protection.
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