| US 7,592,240 B2 | ||
| Method for forming a gate structure through an amorphous silicon layer and applications thereof | ||
| Jen Chieh Chang, Hsinchu (Taiwan); Shih-Chi Lai, Hsinchu (Taiwan); Yi Fu Chung, Hsinchu (Taiwan); and Tun-Fu Hung, Hsinchu (Taiwan) | ||
| Assigned to Mosel Vitelic, Inc., Hsinchu (Taiwan) | ||
| Filed on Aug. 12, 2005, as Appl. No. 11/202,698. | ||
| Claims priority of application No. 93125517 A (TW), filed on Aug. 26, 2004. | ||
| Prior Publication US 2006/0046364 A1, Mar. 02, 2006 | ||
| Int. Cl. H01L 21/20 (2006.01) | ||
| U.S. Cl. 438—482 [438/657; 257/E21.197] | 27 Claims |
| 1. A fabrication method for forming a gate structure through an amorphous silicon layer, comprising:
providing a semiconductor substrate layer;
forming a gate dielectric layer;
forming an undoped amorphous silicon layer on the semiconductor substrate layer at a reaction temperature between about 520°
C. and 560° C.; and
forming a doped amorphous silicon layer by doping an upper portion of the undoped amorphous silicon layer at a reaction temperature
between about 520° C. and 560° C.
|