| US 7,587,545 B2 | ||
| Shared memory device | ||
| Motofumi Kashiwaya, Tokyo (Japan); Takeshi Yamazaki, Kanagawa (Japan); and Hiroshi Hayashi, Kanagawa (Japan) | ||
| Assigned to Sony Corporation, Tokyo (Japan); and Sony Computer Entertainment Inc., Tokyo (Japan) | ||
| Filed on Sep. 01, 2006, as Appl. No. 11/514,202. | ||
| Claims priority of application No. 2005-257074 (JP), filed on Sep. 05, 2005. | ||
| Prior Publication US 2007/0067579 A1, Mar. 22, 2007 | ||
| Int. Cl. G06F 13/00 (2006.01) | ||
| U.S. Cl. 710—317 [711/5; 711/106; 365/230.03] | 27 Claims |
| 1. A shared memory device comprising:
at least one processing module including at least one input/output part;
a first connected interconnect arranged in a first direction;
a second connection interconnect arranged in a second direction substantially perpendicularly intersecting the first direction;
at least two memory systems arranged in both sides of the first connection interconnect, and accessible by the processing
module; wherein
each memory system includes
a memory macro including a plurality of memory banks arranged in the first direction,
a memory interface arranged in the second direction, and wherein;
the input/output part of the processing module, each memory interface and each memory bank in each memory macro are connected
by the first and second connection interconnects, so as to shape in a matrix form above the plurality of memory macros.
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