| US 7,586,201 B2 | ||
| Wiring modeling technique | ||
| Kenta Yamada, Tokyo (Japan) | ||
| Assigned to NEC Electronics Corporation, Kanagawa (Japan) | ||
| Filed on Sep. 24, 2002, as Appl. No. 10/252,610. | ||
| Claims priority of application No. 2001/295987 (JP), filed on Sep. 27, 2001. | ||
| Prior Publication US 2003/0057571 A1, Mar. 27, 2003 | ||
| Int. Cl. H01L 23/52 (2006.01) | ||
| U.S. Cl. 257—786 [716/5] | 6 Claims |
| 1. In a semiconductor device having wirings, a wiring modeling technique comprising the steps of selecting an arbitrary region of said semiconductor device; calculating a wiring area ratio of said wirings to said region; and determining said region and said wiring area ratio to model the cross-sectional profile of a target wiring located in the middle of said region. |