| US 7,580,443 B2 | ||
| Clock generating method and clock generating circuit | ||
| Yasuhiro Uemura, Sagamihara (Japan); Takashi Nakamura, Kokubunji (Japan); Akio Katsushima, Kodaira (Japan); and Makoto Funatsu, Akiruno (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Jan. 13, 2006, as Appl. No. 11/331,154. | ||
| Claims priority of application No. 2005-007422 (JP), filed on Jan. 14, 2005. | ||
| Prior Publication US 2006/0176933 A1, Aug. 10, 2006 | ||
| Int. Cl. H04B 1/69 (2006.01) | ||
| U.S. Cl. 375—130 [375/376; 375/156; 331/10; 331/11; 331/17; 327/156] | 4 Claims |
| 1. A clock generating circuit comprising:
a PLL (Phase-Locked Loop) circuit and a modulator,
wherein a frequency dividing ratio of a feedback-purpose frequency divider in said PLL circuit is changed in accordance with
modulation data produced based upon a modulation profile of said modulator to perform a frequency modulation whereby a spectrum
is spread,
wherein said modulator comprises a multiple modulation profile generating circuit, and moves a turning point of said modulation
profile so as to disperse a degree of frequency,
wherein said modulator further comprises:
a ΔΣbit converting circuit; and
a modulation factor switching circuit,
wherein said ΔΣbit converting circuit performs a pulse width modulation by which a multiple modulation profile outputted by
said multiple modulation profile generating circuit is converted into 1 bit, and
wherein said modulation factor switching circuit switches a frequency spread width which is determined based upon both the
frequency dividing ratio of said feedback-purpose frequency divider and a value which is added to said frequency dividing
ratio in response to the output of said ΔΣbit converting circuit.
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