| US 7,579,229 B2 | ||
| Semiconductor device and semiconductor substrate | ||
| Nobuyuki Sugii, Tokyo (Japan); Kiyokazu Nakagawa, Sayama (Japan); Shinya Yamaguchi, Mitaka (Japan); and Masanobu Miyao, Fukuoka (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Jan. 22, 2008, as Appl. No. 12/10,123. | ||
| Application 12/010123 is a continuation of application No. 10/920432, filed on Aug. 18, 2004, abandoned. | ||
| Application 10/920432 is a continuation of application No. 09/536446, filed on Mar. 28, 2000, abandoned. | ||
| Claims priority of application No. 11-087831 (JP), filed on Mar. 30, 1999. | ||
| Prior Publication US 2008/0206961 A1, Aug. 28, 2008 | ||
| Int. Cl. H01L 21/762 (2006.01) | ||
| U.S. Cl. 438—199 [438/455; 257/19; 257/E21.567] | 7 Claims |
| 1. A method of manufacturing a semiconductor device having p-MOS and n-MOS transistors, the method comprising:
(a) forming a Si1-xGex strain applying layer, which is substantially strain relaxed and has an in-plane lattice constant larger than that of unstrained
Si within a range of proportions greater than 0% and less than 4% on a semiconductor substrate, where 0<x<1;
(b) growing a strained Si layer on said Si1-xGex strain applying layer, thereby forming said strained Si layer which is subjected to in-plane tensile strain;
(c) forming a SiO2 layer on a surface of said strained Si layer;
(d) bonding said SiO2 layer and a supporting substrate to each other;
(e) removing said semiconductor substrate, said Si1-xGex strain applying layer and a part of said strained Si layer, thereby forming an SOI substrate composed of a stack of said supporting
substrate, said SiO layer and said strained Si layer; and
(f) forming said p-MOS and n-MOS transistor on a surface of said strained Si layer.
|