| US 7,573,393 B2 | ||
| Integrated fault output/fault response delay circuit | ||
| David J. Haas, Weare, N.H. (US); Jonathan Lamarre, Pembroke, N.H. (US); and Michael C. Doogue, Manchester, N.H. (US) | ||
| Assigned to Allegro Microsystems, Inc., Worcester, Mass. (US) | ||
| Filed on Feb. 08, 2007, as Appl. No. 11/672,739. | ||
| Prior Publication US 2008/0191865 A1, Aug. 14, 2008 | ||
| Int. Cl. G08B 21/00 (2006.01); H02H 3/00 (2006.01); G01R 31/14 (2006.01) | ||
| U.S. Cl. 340—635 [340/641; 340/650; 340/653; 324/509; 324/537; 361/94] | 6 Claims |
| 4. A time delay fault device comprising:
an integrated circuit (IC) comprising:
an electronic circuit having a fault indicator signal output;
a time delay circuit having an input connected to the fault indicator signal output and an output to provide a delayed fault
indicator signal output, wherein the time delay circuit is responsive to an external reference signal from a resistor capacitor
network coupled to the delayed fault indicator signal output to set the time delay of the delayed fault indicator signal,
the time delay circuit comprising:
a fixed current source to ground that toggles with an internal fault signal;
a field effect transistor having a gate, a drain connected to ground, and a source connected to the output of the time delay
circuit;
a latch having an input and a switchable output connected to the gate of the field effect transistor;
a comparator having an output connected the input of the latch and a first and a second input, the first input connected to
an internal reference signal and the second input connected to the output of the time delay circuit.
|