| US 7,573,291 B1 | ||
| Programmable logic device with enhanced logic block architecture | ||
| Om Agrawal, Los Altos, Calif. (US); Manish Garg, San Jose, Calif. (US); Chan-Chi Jason Cheng, Fremont, Calif. (US); Satwant Singh, Fremont, Calif. (US); and Ju Shen, San Jose, Calif. (US) | ||
| Assigned to Lattice Semiconductor Corporation, Hillsboro, Oreg. (US) | ||
| Filed on Nov. 02, 2007, as Appl. No. 11/934,711. | ||
| Application 11/934711 is a continuation of application No. 11/200983, filed on Aug. 09, 2005, granted, now 7,295,035. | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H03K 19/177 (2006.01) | ||
| U.S. Cl. 326—38 [326/41] | 22 Claims |
| 1. A programmable logic block within a programmable logic device, comprising:
at least two interconnected slices, each of the interconnect slices including at least two interconnected lookup tables, each
lookup table (LUT) adapted to receive input signals from a routing structure and to provide a LUT output signal,
wherein at least a first slice includes a register adapted to register the LUT output signal of a lookup table as an output
signal of the slice and at least a second slice includes fewer such registers than lookup tables.
|