a centrally located chip active area having a perimeter comprising at least a section of an ultra-low-k dielectric layer; and

a crack trapping structure, the structure arranged around the perimeter of the chip, outside the centrally located active area, and operationally disconnected from the chip active area; wherein the crack trapping structure comprises a via-bar structure sandwiched between two metal plates; wherein the via-bar structure comprises a plurality of walls and a plurality of holes, wherein each wall extends between said two metal plates and is selected from the group consisting of metal walls and ceramic walls; and wherein the via-bar structure does not extend to the end of the metal plates near an edge of the chip, the via-bar structure being recessed from the ends of the metal plates by a distance which is greater than the distance between the two metal plates; whereby a crack generated at the edge of the chip and propagating through the ultra-low-k dielectric layer is substantially completely absorbed by the crack trapping structure.