| US 7,572,701 B2 | ||
| Recessed gate for a CMOS image sensor | ||
| James W. Adkisson, Jericho, Vt. (US); John Ellis-Monaghan, Grand Isle, Vt. (US); Mark D. Jaffe, Shelburne, Vt. (US); and Jerome B. Lasky, Essex Junction, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Apr. 13, 2007, as Appl. No. 11/735,223. | ||
| Application 11/735223 is a division of application No. 10/905097, filed on Dec. 15, 2004, granted, now 7,217,968. | ||
| Prior Publication US 2007/0184614 A1, Aug. 09, 2007 | ||
| Int. Cl. H01L 21/02 (2006.01); H01L 31/113 (2006.01) | ||
| U.S. Cl. 438—259 [438/57; 257/291; 257/249; 257/222] | 12 Claims |
| 1. A method of forming an active pixel sensor (APS) cell structure comprising the steps of:
a. etching a trench into a semiconductor substrate to define a recessed portion of said APS cell structure below a substrate
surface;
b. forming a layer of dielectric material over said recessed portion;
c. filling said recessed portion with a conductive material atop said dielectric material layer to form a gate conductor;
d. forming a doped pinning layer comprising material of a first conductivity type in said substrate at a first side of said
gate conductor;
e. forming a doped collection well layer comprising material of a second conductivity type beneath said doped pinning layer;
and,
f. forming a doped diffusion layer of a second conductivity type in said substrate having at least a portion formed at said
surface of said substrate and adjacent a second side of said gate conductor, said recessed portion of said gate conductor
forming a channel region enabling charge transfer between said collection well layer and said diffusion region,
wherein said recessed portion of an image cell transfer gate extends to a depth below the formed doped collection well layer
such that the doped collection well layer intersects said channel region to thereby eliminate any potential baffler interference
to charge transfer caused by said formed pinning layer.
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