	US 7,552,408 B2
	Method for performing design rule check on mask pattern data for an integrated circuit
Cheehoe Teh, Sunnyvale, Calif. (US); Nimcho Lam, Saratoga, Calif. (US); and Mau Truong, Milpitas, Calif. (US)
Assigned to United Microelectronics Corporation, Hsinchu (Taiwan)
Filed on Nov. 05, 2004, as Appl. No. 10/982,650.
Application 10/982650 is a continuation of application No. 10/101648, filed on Mar. 20, 2002, granted, now 6,816,997.
Claims priority of provisional application 60/278672, filed on Mar. 20, 2001.
Prior Publication US 2005/0086619 A1, Apr. 21, 2005
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 17/50 (2006.01)

U.S. Cl. 716—5 [716/19]

22 Claims

1. In a computer readable medium storing a plurality of design rule check instructions, wherein the design rule check instructions being performed on a layout for an electronic circuit embodied on a substrate, the design rule check instructions comprising the steps of:

(a) providing at least a first set of design rules for a first region of the layout within a first layer, including a first minimum spacing between first signal lines situated over the substrate;

(b) providing at least a second set of design rules for a second region of the layout within the first layer including a second minimum spacing between second signal lines situated over the substrate; wherein said first region and said second region correspond to different types of circuitry to be embodied in the electronic circuit, and said first minimum spacing differs from said second minimum spacing;

(c) processing a layer of the layout such that any said first region is checked in accordance with at least said first set of design rules, and said second region is checked in accordance with at least said second set of design rules; and

generating said second set of design rules by modifying said first set of design rules in accordance with differences in sizings, spacings and/or tolerances manufacturable between said first region and said second region.