| US 7,552,318 B2 | ||
| Branch lookahead prefetch for microprocessors | ||
| Richard James Eickemeyer, Rochester, Minn. (US); Hung Qui Le, Austin, Tex. (US); Dung Quoc Nguyen, Austin, Tex. (US); Benjamin Walter Stolt, Austin, Tex. (US); and Brian William Thompto, Austin, Tex. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Dec. 17, 2004, as Appl. No. 11/16,200. | ||
| Prior Publication US 2006/0149933 A1, Jul. 06, 2006 | ||
| Int. Cl. G06F 9/00 (2006.01) | ||
| U.S. Cl. 712—237 [712/219] | 18 Claims |
| 1. A microprocessor which commits results of non-speculative instructions to at least one architected facility, comprising:
multiple execution units;
architected registers which store operand data used by said execution units;
dispatch logic which detects the occurrence of a stall condition during execution of program instructions by said execution
units, speculatively executes one or more pending instructions which include at least one branch instruction during the stall
condition, determines the validity of data utilized by the speculative execution, and maintains a vector of dirty bits to
track the validity of the pending instructions, wherein dirty bits in the vector are initially set to “0” and a given one
of the dirty bits is set to “1” when a corresponding instruction passes a writeback stage where a result calculated by one
of said execution units is provided to one of said architected registers;
an instruction queue; and
a branch prediction unit which predicts a path of the branch instruction prior to said detecting of the occurrence of the
stall condition, and fetches predicted instructions from the predicted path into said instruction queue, wherein said dispatch
logic speculatively flushes the predicted instructions from the instruction queue in response to said executing of the branch
instruction when the dirty bit for the branch instruction is set to “0”.
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