	US 7,552,249 B2
	Direct memory access circuit and disk array device using same
Hidenori Takahashi, Kawasaki (Japan); Yuichi Ogawa, Kawasaki (Japan); and Terumasa Haneda, Kawasaki (Japan)
Assigned to Fujitsu Limited, Kawasaki (Japan)
Filed on Sep. 30, 2005, as Appl. No. 11/239,069.
Claims priority of application No. 2004-372441 (JP), filed on Dec. 24, 2004.
Prior Publication US 2006/0143329 A1, Jun. 29, 2006
Int. Cl. G06F 3/00 (2006.01); G06F 13/28 (2006.01)

U.S. Cl. 710—22 [710/1]

20 Claims

1. A DMA circuit for reading descriptors for indicating DMA transfer content written by a data processing unit, reading data in an address defined by a descriptor from memory, and transferring the data, comprising:

a first register for storing a top pointer which indicates a top descriptor written in said memory by said data processing unit;

a second register for storing a bottom pointer which indicates a position of a next target descriptor of the DMA transfer in a plurality of DMA transfer descriptors in said memory written by said data processing unit;

a transfer circuit for reading the next target descriptor indicated by said bottom pointer from said plurality of DMA transfer descriptors in said memory, each of said plurality of DMA transfer descriptors being written to said memory by adding a descriptor pointer indicating a descriptor number in each of said plurality of DMA transfer descriptors, analyzing the next target descriptor thus read, reading data in an address specified by said next target descriptor of said memory, and transferring the data; and

a comparison circuit for comparing said descriptor pointer indicating the descriptor number written in the read next target descriptor by the data processing unit and said bottom pointer, and controlling the transfer operation of said transfer circuit;

wherein said transfer circuit updates the second register for storing said bottom pointer after completing a data transfer by reading and analyzing one of the descriptors.