| US 7,551,475 B2 | ||
| Data shifting through scan registers | ||
| Vikas Agarwal, Austin, Tex. (US); Sam Gat-Shang Chu, Round Rock, Tex. (US); and Hung Qui Le, Austin, Tex. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Apr. 03, 2006, as Appl. No. 11/278,439. | ||
| Prior Publication US 2007/0240023 A1, Oct. 11, 2007 | ||
| Int. Cl. G11C 11/00 (2006.01); G11C 19/00 (2006.01) | ||
| U.S. Cl. 365—154 [365/201; 714/729] | 3 Claims |
| 1. In a scan chain of registers including a plurality of first cells numbered according to a formula 2n and a plurality of
second cells numbered according to a formula 2n+1, wherein n represents a non-negative integer, an output of a first 2n cell
of the plurality of first cells being communicatively connected to an input of a second 2n+1 cell of the plurality of second
cells, a method of controlling data flow comprising:
selecting a mode of operation for control signals and clock signals that enable the transfer of bits stored in the plurality
of first cells to the plurality of second cells, the mode of operation being one of a scan mode and a flush mode;
responsive to the selection of a flush mode, enabling a shift enable signal and a function clock signal in a control circuit;
generating an output from the control circuit, based on the enabled control circuit signals, that enables the second 2n+1
cell to receive an output bit stored in the first 2n cell, while the input to another first 2n cell directly connected to
and numerically greater than the second 2n+1 cell is disabled, wherein the generating comprises:
logically anding the shift enable signal with the function clock signal to form a first output within the control circuit;
logically oring the first output within the control circuit with a first scan clock signal input to the control circuit to
form the output from the control circuit, the first scan clock signal being disabled in the flush mode; and
operating the control circuit output responsive to logic voltages on the shift enable signal, the function clock signal, and
the first scan clock signal, wherein the control circuit outputs a binary one when the function clock signal and the shift
enable signal are both a binary one; and
flushing, based on the enabling, the bits stored in the plurality of first 2n cells to the plurality of second 2n+1 cells.
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