| US 7,551,473 B2 | ||
| Programmable resistive memory with diode structure | ||
| Hsiang-Lan Lung, Elmsford, N.Y. (US); Chung Hon Lam, Peekskill, N.Y. (US); and Matthew J. Breitwisch, Yorktown Heights, N.Y. (US) | ||
| Assigned to Macronix International Co., Ltd., Hsinchu (Taiwan) | ||
| Filed on Oct. 12, 2007, as Appl. No. 11/871,813. | ||
| Prior Publication US 2009/0095948 A1, Apr. 16, 2009 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—148 [257/2; 257/4; 257/5; 257/8; 438/102] | 25 Claims |
| 1. An integrated circuit with an array of nonvolatile memory cells, comprising:
conductive columns conductively coupled to the nonvolatile memory cells, the conductive columns arranged in parallel and defining
a first planar orientation;
conductive rows conductively coupled to the nonvolatile memory cells, the conductive rows arranged in parallel and defining
a second planar orientation parallel with the first planar orientation;
a nonconductive layer separating the conductive columns from diode structures;
the diode structures connecting programmable resistive elements with the conductive rows, each including:
a first terminal having an exterior surface, and an interior surface connected to at least one of the programmable resistive
elements;
a second terminal in contact with a junction area on the exterior surface of the first terminal providing a diode junction
oriented orthogonal to the first and second planar orientations; and
the programmable resistive elements each having:
a sidewall surface connected to the interior surface of the first terminal of at least one of the diode structures; and
a bottom surface conductively coupled to at least one of the conductive columns.
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