| US 7,551,019 B2 | ||
| Semiconductor integrated circuit and source voltage/substrate bias control circuit | ||
| Tetsuya Fujita, Kanagawa (Japan); Mototsugu Hamada, Palo Alto, Calif. (US); and Hiroyuki Hara, Kanawaga (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jun. 18, 2007, as Appl. No. 11/764,605. | ||
| Application 11/764605 is a division of application No. 10/899004, filed on Jul. 27, 2004, granted, now 7,245,177. | ||
| Claims priority of application No. 2003-372615 (JP), filed on Oct. 31, 2003. | ||
| Prior Publication US 2007/0236276 A1, Oct. 11, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G05F 3/16 (2006.01); H03L 1/00 (2006.01) | ||
| U.S. Cl. 327—537 [327/535] | 9 Claims |
| 1. A semiconductor integrated circuit comprising:
a semiconductor substrate;
a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other;
a plurality of MOS transistors formed in each well region; and
a plurality of substrate bias generators each of which corresponds to one of the plurality of well regions, substrate biases
being applied by the substrate bias generators being no less than a first power supply voltage and no more than a second power
supply voltage, wherein each substrate bias generator comprises:
a controller including a storage portion storing a corresponding one of values of the substrate biases;
a DA converter outputting an analogue signal that depends on the corresponding one of the values of the substrate biases transmitted
from the controller; and
an operation amplifier amplifying a potential difference between the analogue signal and a corresponding predetermined reference
voltage to output a corresponding one of the substrate biases.
|