| US 7,550,759 B2 | ||
| Capacitive single-electron transistor | ||
| Pertti Hakonen, Helsinki (Finland); Mika Sillanpaa, Espoo (Finland); and Leif Roschier, Vantaa (Finland) | ||
| Assigned to MagiQ Technologies, Inc., New York, N.Y. (US) | ||
| Appl. No. 11/630,014 PCT Filed Jul. 18, 2005, PCT No. PCT/FI2005/000331 § 371(c)(1), (2), (4) Date Dec. 18, 2006, PCT Pub. No. WO2006/008335, PCT Pub. Date Jan. 26, 2006. |
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| Claims priority of application No. 20041000 (FI), filed on Jul. 19, 2004. | ||
| Prior Publication US 2007/0263432 A1, Nov. 15, 2007 | ||
| Int. Cl. G01R 29/00 (2006.01); H01L 29/06 (2006.01) | ||
| U.S. Cl. 257—24 [324/157; 324/158.1] | 9 Claims |
| 1. A method of determining a phase of a qubit having states defined by different phases, comprising:
establishing the qubit in a superconducting single-electron transistor (SSET) having a gate, a ground and a capacitance;
measuring the capacitance of the SSET between the gate and ground; and
determining the phase from the measured gate-to-ground capacitance.
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