| US 7,550,389 B1 | ||
| Dual damascene method of forming a metal line of semiconductor device | ||
| Chang Jun Yoo, Gyeonggi-do (Korea, Republic of); and Ga Young Ha, Gyeonggi-do (Korea, Republic of) | ||
| Assigned to Hynix Semiconductor Inc., Kyoungki-do (Korea, Republic of) | ||
| Filed on Jun. 11, 2008, as Appl. No. 12/136,904. | ||
| Claims priority of application No. 10-2008-0037742 (KR), filed on Apr. 23, 2008. | ||
| Int. Cl. H01L 21/311 (2006.01) | ||
| U.S. Cl. 438—700 [438/734] | 8 Claims |
| 1. A method of forming a metal line of a semiconductor device, the method comprising the steps of:
forming a spin-on dielectric (SOD) layer to fill a contact hole on an insulation layer of the semiconductor device;
partially annealing the SOD layer to selectively bake upper portions of the SOD layer which are filled in an upper portion
of the contact hole and placed on the insulation layer;
etching exposed portions of the baked upper portions of the SOD layer to define a trench; and
cleaning the trench by removing an unbaked portion of the SOD layer which is filled in a lower portion of the contact hole.
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