| US 7,515,466 B2 | ||
| Method for controlling semiconductor storage device comprising memory cells each configured to hold multi-bit data, and memory card provided with semiconductor storage device | ||
| Tomoji Takada, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Mar. 27, 2007, as Appl. No. 11/691,799. | ||
| Claims priority of application No. 2006-086241 (JP), filed on Mar. 27, 2006. | ||
| Prior Publication US 2007/0245098 A1, Oct. 18, 2007 | ||
| Int. Cl. G11C 11/03 (2006.01) | ||
| U.S. Cl. 365—185.03 [365/185.22; 365/189.04; 365/230.08; 365/233.1] | 14 Claims |
| 1. A method for controlling a semiconductor storage device including a plurality of memory cells each configured to hold data
of 2 bits or more, the method comprising:
starting first signal processing and inputting lower bits of the data into the semiconductor storage device by a control unit,
in response to the semiconductor storage device having been set in a ready state to receive the data;
starting second signal processing and inputting upper bits of the data into the semiconductor storage device by the control
unit, in response to the semiconductor storage device having been changed into the ready state from a busy state to reject
input of the data, at or by an end of writing the lower bits to the memory cells; and
finishing the second signal processing by the control unit, at or by an end of writing the upper bits to the memory cells,
a period necessary for said writing the upper bits being longer than a period necessary for said writing the lower bits, a
period necessary for performing the second signal processing being longer than a period necessary for performing the first
signal processing.
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