	US 7,515,126 B2
	Driving circuit for display device, and display device
Takahiro Senda, Tenri (Japan); and Akira Tagawa, Nara (Japan)
Assigned to Sharp Kabushiki Kaisha, Osaka (Japan)
Filed on Aug. 27, 2004, as Appl. No. 10/929,058.
Claims priority of application No. 2003-209331 (JP), filed on Aug. 28, 2003; and application No. 2004-186969 (JP), filed on Jun. 24, 2004.
Prior Publication US 2005/0046619 A1, Mar. 03, 2005
Int. Cl. G09G 3/30 (2006.01); G09G 3/32 (2006.01); G09G 3/36 (2006.01)

U.S. Cl. 345—77 [345/82; 345/98]

9 Claims

1. A driving circuit for driving a pixel circuit in a display device that includes a plurality of scan lines, at least one data line, and the pixel circuit, wherein the pixel circuit includes an electro-optic element and is disposed in a matrix at each intersection of the scan lines and the at least one data line, said driving circuit comprising:

a signal output circuit connected to each data line so as to hold a current value of a reference ON signal that turns on the electro-optic element, said signal output circuit outputting the ON signal to the at least one data line with a current value held according to ON data, and outputting an OFF signal to the at least one data line so as to turn off the electro-optic element according to OFF data; and

a control circuit which controls the hold operation of the signal output circuit so as to enable the ON signal to reset its current value within a blanking period in which a display state of all pixel circuits on a selected scan line is set to a non-display state; wherein

the signal output circuit holds at least one current value of the ON signal; and

the signal output circuit includes:

first and second transistors having gate terminals that are connected to each other, and having input terminals that are connected to a common power line;

a capacitor connected between the input terminals and the gate terminals of the first and second transistors; and

a third transistor having one of an input terminal and an output terminal connected to an output terminal of the first transistor; wherein

the capacitor and the first through third transistors include a current mirror structure in which a voltage according to a current that flows through the first transistor is held in the capacitor by controlling a gate voltage of the third transistor with the control circuit, and the held voltage is used to flow a current of the same current value to the first and second transistors.