| US 7,514,797 B2 | ||
| Multi-die wafer level packaging | ||
| Chen-Shien Chen, Zhubei (Taiwan); Kai-Ming Ching, Jhudong Township (Taiwan); Chih-Hua Chen, Taipei (Taiwan); and Chen-Cheng Kuo, Chu-Pei (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (Taiwan) | ||
| Filed on May 31, 2007, as Appl. No. 11/756,347. | ||
| Prior Publication US 2008/0296763 A1, Dec. 04, 2008 | ||
| Int. Cl. H01L 23/48 (2006.01) | ||
| U.S. Cl. 257—777 [257/774] | 19 Claims |
| 1. A semiconductor package comprising:
a first die having a first surface and a second surface opposite the first surface;
vias through the first die;
a first set of redistribution lines electrically coupling semiconductor components of the first die to the vias; and
a second die having a first surface and a second surface opposite the first surface, the first surface of the second die having
contact pads, the first set of redistribution lines electrically coupling the contact pads of the second die to the vias.
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