| US 7,514,749 B2 | ||
| Semiconductor device and a method of manufacturing the same | ||
| Kunihiko Kato, Tokyo (Japan); Masami Koketsu, Tokyo (Japan); Shigeya Toyokawa, Tokyo (Japan); Keiichi Yoshizumi, Tokyo (Japan); Hideki Yasuoka, Tokyo (Japan); and Yasuhiro Takeda, Tokyo (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on May 18, 2008, as Appl. No. 12/122,717. | ||
| Application 12/122717 is a division of application No. 11/405540, filed on Apr. 18, 2006, granted, now 7,391,083. | ||
| Claims priority of application No. 2005-121974 (JP), filed on Apr. 20, 2005. | ||
| Prior Publication US 2008/0220580 A1, Sep. 11, 2008 | ||
| Int. Cl. H01L 23/62 (2006.01) | ||
| U.S. Cl. 257—360 [257/392; 257/491; 257/E27.067; 438/218] | 7 Claims |
| 1. A method of manufacturing a semiconductor integrated circuit device having, over one and same semiconductor substrate:
a first MISFET of a first breakdown voltage formed in a first region; and a second MISFET of a second breakdown voltage lower
than the first breakdown voltage formed in a second region, the method comprising the steps of:
(a) forming an element isolation region in a main surface of the semiconductor substrate;
(b) introducing an impurity ion into the first region of the semiconductor substrate to form a first semiconductor region
where a source and a drain of the first MISFET are formed;
(c) forming a first gate insulating film over the main surface of the first region of the semiconductor substrate;
(d) depositing a first conductive film over the first gate insulating film and patterning the first conductive film to form
a first gate electrode of the first MISFET in the first region;
(e) after the step (d), forming a second gate insulating film over the main surface of the second region of the semiconductor
substrate;
(f) depositing a second conductive film over the second gate insulating film and patterning the second conductive film to
form a second gate electrode of the second MISFET in the second region; and
(g) introducing an impurity ion into the second region of the semiconductor substrate to form a third semiconductor region
serving as a source and a drain of the second MISFET,
wherein the element isolation region is disposed under a side wall of the first gate electrode and is formed in such a manner
that the width thereof in a first direction orthogonal to the extending direction of the first gate electrode is larger than
the thickness of the second conductive film in a planar region not overlapping the first gate electrode.
|