| US 7,514,740 B2 | ||
| Logic compatible storage device | ||
| Te-Hsun Hsu, Hsinchu (Taiwan); Yung-Tao Lin, Hsinchu (Taiwan); Derek Lin, Hsinchu (Taiwan); and Jack Yeh, Jhubei (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (Taiwan) | ||
| Filed on Jul. 10, 2006, as Appl. No. 11/483,916. | ||
| Prior Publication US 2008/0006868 A1, Jan. 10, 2008 | ||
| Int. Cl. H01L 27/108 (2006.01); H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—316 [257/296; 257/300; 257/315; 257/532] | 16 Claims |
| 1. A memory cell comprising:
a semiconductor substrate;
a floating gate over the semiconductor substrate;
a first capacitor comprising a first plate, the floating gate, and a dielectric therebetween, the first plate comprising a
first doped region and a second doped region in the semiconductor substrate;
a second capacitor comprising a second plate, the floating gate, and a dielectric therebetween, wherein the second plate of
the second capacitor comprises a third doped region and a fourth doped region in the semiconductor substrate, the third doped
region and the fourth doped region disposed on opposite sides of the floating gate, and the third doped region and the fourth
doped region interconnected by a conductive feature;
a third capacitor comprising a third plate and a fourth plate, wherein the third and fourth plates are formed in respective
metallization layers over the semiconductor substrate, and wherein the third plate is electrically connected to the floating
gate; and
a transistor comprising:
a gate electrode over the semiconductor substrate; and
a first and a second source/drain region substantially aligned with opposite sidewalls of the gate electrode, wherein the
second source/drain region is connected to the first doped region of the first capacitor.
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