| US 7,514,355 B2 | ||
| Multilayer interconnection structure and method for forming the same | ||
| Syuji Katase, Akiruno (Japan); Kouichi Suzuki, Akiruno (Japan); Kenji Chichii, Akiruno (Japan); and Katsuji Tabara, Akiruno (Japan) | ||
| Assigned to Fujitsu Microelectronics Limited, Tokyo (Japan) | ||
| Filed on Jun. 10, 2005, as Appl. No. 11/149,188. | ||
| Claims priority of application No. 2004-187005 (JP), filed on Jun. 24, 2004. | ||
| Prior Publication US 2005/0287800 A1, Dec. 29, 2005 | ||
| Int. Cl. H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 21/44 (2006.01); H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—637 [438/652; 438/667; 257/750; 257/774; 257/E21.597] | 3 Claims |
| 1. A method for producing a multilayer interconnection structure on a semiconductor substrate, said multilayer interconnection
structure includes a diagonal interconnection for connecting between a first interconnection and a second interconnection
and extending along first body diagonal direction with respect to first and second planes, comprising:
recognizing said first body diagonal direction by determining said first interconnection and said second interconnection;
recognizing an angle of said first body diagonal direction from a horizontal plane;
inclining said semiconductor substrate so that said first body diagonal direction becomes vertical;
forming a through hole in a interlayer insulation film between said first interconnection and said second interconnection
along said body diagonal direction by first FIB irradiation; and
filling said through hole with metal material by second FIB irradiation.
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