| US 7,514,348 B2 | ||
| Sidewall coverage for copper damascene filling | ||
| Shau-Lin Shue, Hsinchu (Taiwan); Mei-Yun Wang, Hsin-Chu (Taiwan); and Chen-Hua Yu, Hsin-Chu (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Company, Hsin-Chu (Taiwan) | ||
| Filed on Sep. 25, 2007, as Appl. No. 11/860,639. | ||
| Application 11/860639 is a continuation of application No. 10/733722, filed on Dec. 11, 2003, granted, now 7,282,450. | ||
| Application 10/733722 is a continuation of application No. 09/989802, filed on Nov. 20, 2001, granted, now 6,686,280. | ||
| Application 09/989802 is a continuation in part of application No. 09/358983, filed on Jul. 22, 1999, abandoned. | ||
| Prior Publication US 2008/0009133 A1, Jan. 10, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 21/302 (2006.01) | ||
| U.S. Cl. 438—597 | 12 Claims |
| 1. A dual damascene process comprising:
providing a dielectric layer;
patterning and etching the dielectric layer to form a trench having a bottom surface, a mouth, and side walls;
depositing a seed layer on the dielectric layer, the bottom surface, and the side walls, wherein the depositing results in
an overhang at the mouth of the trench;
reducing the seed layer by an amount to remove at least a portion of the overhang present at the mouth of the trench by a
sputter etching process; and
filling the trench with a conductive material.
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