| US 7,514,296 B2 | ||
| Method for manufacturing semiconductor device | ||
| Shigehisa Tajimi, Shonai (Japan) | ||
| Assigned to Seiko Epson Corporation, (Japan) | ||
| Filed on Mar. 06, 2007, as Appl. No. 11/682,498. | ||
| Claims priority of application No. 2006-060770 (JP), filed on Mar. 07, 2006. | ||
| Prior Publication US 2007/0212814 A1, Sep. 13, 2007 | ||
| Int. Cl. H01L 21/50 (2006.01); H01L 21/48 (2006.01); H01L 21/44 (2006.01) | ||
| U.S. Cl. 438—123 [438/111; 438/112; 438/106] | 7 Claims |

| 1. A method for manufacturing a semiconductor device, comprising:
preparing a wiring board including a base board having a first surface and a second surface, a wiring pattern having electrical
connectors and formed on the first surface, a first resist layer having a first opening for exposing the electrical connectors
and covering at least a part of the first surface and a part of the wiring pattern, and a second resist layer having a second
opening that overlaps with a region where the electrical connectors are formed and covering at least a part of the second
surface;
preparing a semiconductor chip having electrodes; and
performing a bonding operation for electrically coupling the electrical connectors and the electrodes correspondingly by holding
and heating the semiconductor chip with a bonding tool that has a heating mechanism and an end face whose contour is smaller
than that of the second opening, aligning the bonding tool in such a way that the end face only overlaps with a region inside
the second opening on the second surface, and mounting the semiconductor chip on the wiring board with the semiconductor chip
facing the first surface.
|