	US 7,513,037 B2
	Method of embedding components in multi-layer circuit boards
Mark Thomas McCormack, Livermore, Calif. (US); Hunt Hang Jiang, San Jose, Calif. (US); Michael G. Peters, Santa Clara, Calif. (US); and Yasuhito Takahashi, Nagano (Japan)
Assigned to Fujitsu Limited, Kawasaki (Japan)
Filed on Feb. 17, 2005, as Appl. No. 11/60,002.
Application 11/060002 is a division of application No. 09/866092, filed on May 23, 2001.
Prior Publication US 2005/0153060 A1, Jul. 14, 2005
Int. Cl. H01K 3/10 (2006.01)

U.S. Cl. 29—852 [29/830; 29/832; 29/847; 174/262; 438/107]

11 Claims

1. A method for producing a circuit board having an integrated electronic component comprising:

providing a circuit board substrate having a first substrate surface and a second substrate surface;

securing a first integrated electronic component to the first substrate surface;

disposing a first dielectric layer on the first substrate surface and over the first integrated electronic component;

disposing a metallic layer on the first dielectric layer to produce an integrated electronic component assembly comprising the circuit board substrate, the first integrated electronic component, first dielectric layer, and the metallic layer;

producing in the integrated electronic component assembly at least one via, said via passing through said circuit board substrate from said first substrate surface to said second substrate surface and passing through the first dielectric layer, and the metallic layer;

forming a metal lining in said via in contact with said metallic layer;

disposing a second dielectric layer over said via and over said metallic layer;

producing at least one opening in the second dielectric layer and in the first dielectric layer to expose at least part of the first integrated electronic component; and

forming a metal lining in said opening and coupled to the first integrated electronic component to produce a circuit board having at least one integrated electronic component.