| US 7,477,257 B2 | ||
| Apparatus, system, and method for graphics memory hub | ||
| Joseph David Greco, San Jose, Calif. (US); Jonah M. Alben, San Jose, Calif. (US); Barry A. Wagner, San Jose, Calif. (US); and Anthony Michael Tamasi, Los Gatos, Calif. (US) | ||
| Assigned to Nvidia Corporation, Santa Clara, Calif. (US) | ||
| Filed on Dec. 15, 2005, as Appl. No. 11/303,187. | ||
| Prior Publication US 2007/0139426 A1, Jun. 21, 2007 | ||
| Int. Cl. G09G 5/39 (2006.01); G06F 13/28 (2006.01); G06F 13/00 (2006.01); G06F 13/14 (2006.01) | ||
| U.S. Cl. 345—531 [345/533; 345/536; 345/520; 711/111; 711/154] | 19 Claims |
| 1. A memory hub for a graphics system, comprising:
a dynamic random access memory (DRAM) interface operative to access a plurality of different types of DRAM memories each requiring
a different DRAM protocol;
a hub interface for accessing the memory hub via an Input/Output (I/O) bus; and
logic for bridging signals between said hub interface and said DRAM interface and performing translation of signals between
said hub interface and said DRAM interface;
said memory hub operative for a graphics processing unit (GPU) to utilize said hub interface to access two or more DRAMs;
wherein said hub interface utilizes a high speed packetized bus protocol and said DRAM interface utilizes a non-packetized
protocol, said high speed packetized bus protocol having at least a factor of two faster transfer rate than said non-packetized
protocol such that said memory hub reduces an I/O pin count on said GPU.
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