| US 7,477,074 B1 | ||
| Multiple data rate interface architecture | ||
| Philip Pan, Fremont, Calif. (US); Chiakang Sung, Milpitas, Calif. (US); Joseph Huang, San Jose, Calif. (US); Yan Chong, Mountain View, Calif. (US); and Bonnie I. Wang, Cupertino, Calif. (US) | ||
| Assigned to Altera Corporation, San Jose, Calif. (US) | ||
| Filed on Dec. 11, 2006, as Appl. No. 11/609,249. | ||
| Application 11/609249 is a continuation of application No. 11/059299, filed on Feb. 15, 2005, granted, now 7,167,023. | ||
| Application 11/059299 is a continuation of application No. 10/623394, filed on Jul. 18, 2003, granted, now 6,946,872. | ||
| Application 10/623394 is a continuation of application No. 10/038737, filed on Jan. 02, 2002, granted, now 6,806,733. | ||
| Claims priority of provisional application 60/315879, filed on Aug. 29, 2001. | ||
| Int. Cl. H01L 25/00 (2006.01); H03K 19/177 (2006.01) | ||
| U.S. Cl. 326—41 [326/39; 326/47] | 20 Claims |
| 1. An integrated circuit comprising:
a plurality of programmable logic elements configurable to perform user-defined functions;
a first I/O bank comprising:
a plurality of I/O register blocks, each I/O register block having an input coupled to one of a plurality of pads; and
a delay block having an input coupled to one of the plurality of pads and an output coupled to a clock input for each of the
plurality of I/O register blocks;
a second I/O bank comprising a plurality of LVDS inputs;
a third I/O bank comprising a plurality of LVDS outputs; and
a plurality of programmable interconnect lines, configurable to couple the plurality of programmable logic elements to the
first, second, and third I/O banks.
|