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CLASS 710,	ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS: INPUT/OUTPUT
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SECTION I - CLASS DEFINITION

This class provides, within a computer or digital data processing system, for the following subject matter:

A. Processes or apparatus for transferring data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, or further transfer or for transferring data from the computers or digital data processing systems to the peripherals;

B. Processes or apparatus for interconnecting or communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system;

C. Processes or apparatus for preventing access to a shared resource of a computer or digital data processing system;

D. Processes or apparatus for granting access to a shared resource of a computer of digital data processing system by one of a plurality of components of the computer or digital data processing system by interrogating each of the components in a predetermined order;

E. Processes or apparatus for determining which of a plurality of components of a computer or digital data processing system contending for access to a shared resource shall be granted access at any one time based upon a predetermined criteria; and

F. Processes or apparatus for stopping, halting, or suspending a current processing function within a computer or digital data processing system.

SECTION II - REFERENCES TO OTHER CLASSES

SEE OR SEARCH CLASS:

SECTION III - GLOSSARY

BUS

A conductor used for transferring data, signals, or power.

COMPUTER

A machine that inputs data, processes data, stores data, and outputs data.

DATA

Representation of information in a coded manner suitable for communication, interpretation, or processing.

Address data - Data that represent or identify a source or destination.

Instruction data - Data that represent an operation and identify its operands, if any.

Status data - Data that represent conditions of data, computers, peripherals, memory, etc.

User data - Data other than address data, instruction data, or status data.

data processing

See PROCESSING, below.

DIGITAL DATA PROCESSING SYSTEM

An arrangement of processor(s) in combination with either memory or peripherals, or both, performing data processing.

ERROR

Manifestation of a fault as an undesired event that occurs when actual behavior deviates from the behavior that is required by initial specifications.

FAILURE

Manifestation of an error as a nonperformance of an expected system service as required by the initial specifications.

FAULT

A flaw in a functional unit (hardware or software).

INFORMATION

Meaning that a human being assigns to data by means of the conventions applied to that data.

MEMORY

A functional unit to which data can be stored and from which data can be retrieved.

PERIPHERAL

A functional unit that transmits data to or receives data from a computer to which it is coupled.

PROCESSING

Methods or apparatus performing systematic operations upon data or information exemplified by functions such as data or information transferring, merging, sorting, and calculating (i.e., arithmetic operations or logical operations).

PROCESSOR

A functional unit that interprets and executes instruction data.

RECOVERY

Responding to a fault in a system by either returning a system to a previous level of correct operation, achieving a degraded level of correct operation, or safely shutting down the system.

SECURITY

Extent of protection for system hardware, software, or data from maliciously caused destruction, unauthorized modification, or unauthorized disclosure.

SUBCLASSES

1	INPUT/OUTPUT DATA PROCESSING:
	This subclass is indented under the class definition.  Subject matter comprising means or steps for transferring data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, or further transfer or for transferring data from the computers or digital data processing systems to the peripherals. (1) Note. Classification herein requires more than nominal recitation of "peripheral device," "peripheral," "input/output," "I/O," etc. (2) Note. Processes and apparatus for code conversion in transferring codes from a keyboard peripheral to a computer or digital data processing system are classified elsewhere. Code conversion for control of image data for display-including the transferring of data to be displayed via an input peripheral (e.g., keyboard, joystick, mouse, touch tablet, etc.) to a computer or digital data processing system and subsequently transferring image data to a display peripheral via a display memory or display controller are classified elsewhere. Processes and apparatus for code in transmitting data from a facsimile peripheral to a computer (e.g., by a modem) for transmission over a telephone line to another computer (e.g., by a modem) for transmission to another facsimile peripheral are classified elsewhere. See the SEE OR SEARCH CLASS notes below. (3) Note. Processes and apparatus for detecting or correcting errors in generic electrical pulse or pulse coded data transferred from or to peripherals and for detecting and recovering from faults of peripherals, particularly transmission facility testing, memory testing, memory access block coding, bus and I/O channel fault recovery, peripheral fault recovery, and bus or I/O channel error detection or notification are classified elsewhere. See the SEE OR SEARCH CLASS notes below. (4) Note. Processes and apparatus for transferring data to output peripherals for presenting the data on a fixed medium (i.e., a hard copy) are classified elsewhere. See the SEE OR SEARCH CLASS notes below. (5) Note. Processes and apparatus for transferring data between a plurality of computers even if the transferring employs peripherals (e.g., modems, line adapters) are classified elsewhere. See the SEE OR SEARCH CLASS notes below. (6) Note. Processes and apparatus for accessing or controlling memories that are peripherals are classified elsewhere. See the SEE OR SEARCH CLASS notes below. (7) Note. Processes and apparatus for furthering the security of peripherals are classified elsewhere. See the SEE OR SEARCH CLASSnotes below. SEE OR SEARCH THIS CLASS, SUBCLASS: 100+, for transferring data among memories, processors, and buses of a computer. SEE OR SEARCH CLASS: 341,  Coded Data Generation or Conversion,   subclasses 22+ for code conversion in transferring codes from a peripheral keyboard to a computer. 345,  Computer Graphics Processing and Selective Visual Display Systems,   appropriate subclasses for selective electrical control of image data for display, including the transferring of data to be displayed via a peripheral input device (keyboard, joystick, mouse, touch tablet, etc.) to a computer and subsequently transferring image data to a peripheral display device via a display memory/display controller. 358,  Facsimile and Static Presentation Processing,   subclasses 1.1 through 1.18for transferring data to peripherals for presenting the data on a fixed medium and subclasses 400 through 304 for transmitting data from a peripheral facsimile machine to a computer (e.g., by modem) for transmission over a telephone line to another computer (e.g., by modem) for transmission to another peripheral fax machine. 709,  Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring,   appropriate subclasses for transferring data between a plurality of computers even if the transferring employs peripherals (e.g., modems, line adapters, etc.) particularly subclass 212 for computer-to-computer direct memory accessing. 711,  Electrical Computers and Digital Processing Systems: Memory,   appropriate subclasses for accessing, controlling, storing or writing to, retrieving or reading from memories that are peripherals. 714,  Error Detection/Correction and Fault Detection/Recovery,   various subclasses for detecting or correcting errors in generic electrical pulse or pulse coded data and for detecting and recovering from faults of computers, digital data processing systems, and logic level based systems; subclass 43 for bus and I/O channel fault recovery, subclass 44 for peripheral fault recovery, subclass 56 for bus or I/O channel error detection or notification, subclasses 712+ for transmission facility testing, subclasses 718+ for memory testing, and subclasses 763+ for memory access block coding,. 726,  Information Security,   subclasses 1 through 36for information security in computers or digital processing system.

2	Input/Output expansion:
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for increasing the number of the peripherals that can be coupled to the digital data processing system or computer.

3	Input/Output addressing:
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for employing an identifier for the peripheral, digital data processing system or computer in order to transfer data therebetween. SEE OR SEARCH CLASS: 711,  Electrical Computers and Digital Processing Systems: Memory,   subclasses 1+ for addressing combined with specific memory configurations (e.g., extended, expanded, dynamic, etc.) in a digital data processing system, subclasses 100+ for generalized storage accessing and control in a digital data processing system, and subclasses 200+ for generalized address forming in a digital data processing system.

4	Address data transfer:
	This subclass is indented under subclass 3.  Subject matter further comprising means or steps for transferring address data between the peripheral and digital data processing system or computer to ensure that associated user data are transferred to the intended peripheral and digital data processing system or computer.

5	Input/Output command processing:
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for fetching, buffering, decoding, or executing instruction data in order to transfer user data between the peripheral and digital data processing system or computer. (1) Note. This and indented subclasses are directed to command processing for Input/Output operations. The processing control or the processing control for data transfer is classified elsewhere. See the SEE OR SEARCH CLASS notes below. SEE OR SEARCH CLASS: 712,  Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),   subclasses 400+ for processing control, particularly subclass 405 for processing control for data transfer.

6	Operation scheduling:
	This subclass is indented under subclass 5.  Subject matter further comprising means or steps for specifying the order in which the peripheral and digital data processing system or computer perform a function in order to transfer the user data between a peripheral and digital data processing system or computer.

7	Concurrently performing Input/Output operation and other operation unrelated to Input/Output:
	This subclass is indented under subclass 5.  Subject matter further comprising means or steps for performing a non-Input/Output function while also transferring data between the peripheral and digital data processing system or computer.

8	Peripheral configuration:
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for assigning operating characteristics to a peripheral. SEE OR SEARCH THIS CLASS, SUBCLASS: 104, for configuring by utilizing a hardware structure for providing the arrangement of the digital data processing system including characteristics of the digital data processing system"s components to a digital data processing system processor. SEE OR SEARCH CLASS: 711,  Electrical Computers and Digital Processing Systems: Memory,   subclasses 170+ for automatically determining or allocating memory space. 713,  Electrical Computers and Digital Processing Systems: Support,   subclasses 1 , 2, and 100 for digital data processing system initialization and configuration at boot-time.

9	Address assignment:
	This subclass is indented under subclass 8.  Subject matter further comprising means or steps for giving an identifier (i.e., address data) to the peripheral. SEE OR SEARCH THIS CLASS, SUBCLASS: 3, for input/output addressing.

10	Configuration initialization:
	This subclass is indented under subclass 8.  Subject matter further comprising means or steps for automatically assigning an operating characteristic when the peripheral, digital data processing system, or computer is started or reset.

11	Protocol selection:
	This subclass is indented under subclass 8.  Subject matter further comprising means or steps for choosing a data communications protocol to be employed in order to transfer data between the peripheral and digital data processing system or computer.

12	As input or output:
	This subclass is indented under subclass 8.  Subject matter further comprising means or steps for assigning a port or adapter, which is associated with the peripheral, to permit either transferring data from the peripheral to the digital data processing system or computer or from the digital data processing system or computer to the peripheral.

13	By detachable memory:
	This subclass is indented under subclass 8.  Subject matter further comprising means or steps for assigning the operating characteristics based on data stored in a removable memory.

14	Mode selection:
	This subclass is indented under subclass 8.  Subject matter further comprising means or steps for choosing a method of operating for the peripheral.

15	Peripheral monitoring:
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for enabling a digital data processing system or computer to detect or observe an operating characteristic or condition of the peripheral. SEE OR SEARCH CLASS: 379,  Telephonic Communications,   subclasses 32.01 through 33and subclasses 112.01-112.1 for service monitoring and usage monitoring in telephonic communications. 713,  Electrical Computers and Digital Processing Systems: Support,   subclasses 1 , 2, 100 for digital data processing system initialization and configuration at boot-time. 714,  Error Detection/Correction and Fault Detection/Recovery,   subclass 1 for furthering the reliability or availability of peripherals, especially subclasses 5.1 through 6.32 for memory or I/O subsystem affected faults, subclass 43 for bus or I/O channel device fault, subclasses 47.1 through 47.3 for performance monitoring, subclasses 712-717 for transmission facility testing, and subclasses 718-723 for memory testing.

16	Characteristic discrimination:
	This subclass is indented under subclass 15.  Subject matter further comprising means or steps for detecting the connection, type, or configuration of the peripheral.

17	Availability monitoring:
	This subclass is indented under subclass 15.  Subject matter further comprising means or steps for detecting whether the peripheral is available to participate in transferring data with the digital data processing system or computer.

18	Activity monitoring:
	This subclass is indented under subclass 15.  Subject matter further comprising means or steps for detecting the amount or type of usage of the peripheral over a period of time.

19	Status updating:
	This subclass is indented under subclass 15.  Subject matter further comprising means or steps for detecting or reporting change in the condition of a peripheral.

20	Concurrent Input/Output processing and data transfer:
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for performing an additional I/O-related function while also exchanging data between a peripheral and computer. SEE OR SEARCH THIS CLASS, SUBCLASS: 7, for exchanging data between the peripherals and computers while performing tasks unrelated to Input/Output data processing.

21	Concurrent data transferring:
	This subclass is indented under subclass 20.  Subject matter further comprising means or steps for transferring plural groups of data between a peripheral and digital data processing system or computer at the same time.

22	Direct Memory Accessing (DMA):
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for transferring data between a peripheral and memory of a digital data processing system or computer with minimal or no intervention from a main processor of the digital data processing system or computer. (1) Note. Direct Memory Accessing (DMA) appears here for its classical treatment as an I/O operation as opposed to a memory accessing and control operation per se. Memory accessing and control are classified elsewhere. See the SEE OR SEARCH CLASS notes below. (2) Note. Transferring data "directly" between memories of different digital data processing system or computers is classified elsewhere. See the SEE OR SEARCH CLASS notes below. SEE OR SEARCH CLASS: 360,  Dynamic Magnetic Information Storage or Retrieval,   appropriate subclasses for record carriers and systems wherein information is stored and retrieved by interaction with a medium and there is relative motion between a medium and a transducer, for example, magnetic disk drive devices and control thereof, per se. 709,  Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring,   subclass 212 for computer-to-computer direct memory accessing. 711,  Electrical Computers and Digital Processing Systems: Memory,   subclasses 100+ for memory accessing and controlling, per se.

23	Programmed control memory accessing:
	This subclass is indented under subclass 22.  Subject matter further comprising means or steps for transferring data directly between a peripheral and memory and also for transferring data between a peripheral and the memory under control of the central or main processor(s), although not necessarily at the same time.

24	By command chaining:
	This subclass is indented under subclass 22.  Subject matter further comprising means or steps for linking individual instruction data and then executing the linked instruction data to transfer data directly between a peripheral and memory.

25	Timing:
	This subclass is indented under subclass 22.  Subject matter further comprising means or steps for determining when to transfer data directly between a peripheral and memory. SEE OR SEARCH CLASS: 370,  Multiplex Communications,   various subclasses for TDM, FDM, etc., per se. 713,  Electrical Computers and Digital Processing Systems: Support,   subclass 375 for synchronization maintenance of plural processors; subclasses 400-401 for clock synchronization, per se, subclasses 500-503 for digital data processing system clock, pulse and timing interval generation, per se. 718,  Electrical Computers and Digital Processing Systems: Virtual Machine Task or Process Management or Task Management/Control,   appropriate subclassesfor task and process management.

26	Using addressing:
	This subclass is indented under subclass 22.  Subject matter further comprising details of generating or employing address data to transfer data directly between a peripheral and the memory of the digital data processing system or computer. SEE OR SEARCH CLASS: 711,  Electrical Computers and Digital Processing Systems: Memory,   subclasses 1+ for addressing combined with specific memory configurations (e.g., extended, expanded, dynamic, etc.) and subclasses 200+ for generalized address forming.

27	Via separate bus:
	This subclass is indented under subclass 22.  Subject matter wherein plural buses permit a processor to access memories concurrently with direct memory accesses.

28	With access regulating:
	This subclass is indented under subclass 22.  Subject matter further comprising means or steps for directing which of the peripherals may transfer data directly with the memories. SEE OR SEARCH THIS CLASS, SUBCLASS: 107+, for bus access regulating in a digital data processing system. 200-244, for general purpose access regulating in a digital data processing system. 260+, for interrupt processing, per se. SEE OR SEARCH CLASS: 718,  Electrical Computers and Digital Processing Systems: Virtual Machine Task or Process Management or Task Management/Control,   appropriate subclassesfor task and process management. 726,  Information Security,   subclasses 1 through 36for information security in computers or digital processing system.

29	Flow controlling:
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for controlling a first rate at which a peripheral or the digital data processing system and computer transmit data such that the first rate does not exceed a second rate at which the computer or digital data processing system and peripheral can receive data. SEE OR SEARCH CLASS: 709,  Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring,   subclass 233 for transfer speed regulating in computer-to-computer data transferring.

30	Frame forming:
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for arranging data into a specified format in order to transfer the arranged data between a peripheral and a digital data processing system or a computer. SEE OR SEARCH CLASS: 370,  Multiplex Communications,   for the simultaneous transmission of two or more signals over a common medium, particularly subclasses 470+ for adaptive arranging data into variable frame lengths in order to transfer data between systems requiring different frame formats. 709,  Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring,   subclass 236 for computer-to-computer data framing.

31	Transfer direction selection:
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for specifying whether data are to be transmitted from the peripheral to the digital data processing system or computer or from the digital data processing system or computer to the peripheral.

32	Transfer termination:
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for ceasing to exchange data between the peripheral and digital data processing system or computer.

33	Data transfer specifying:
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for defining a characteristic of a desired transfer of data between the peripheral and digital data processing system or computer (e.g., amount of the data to be transferred, location of the data to be transferred). (1) Note. The combination of specifying data transfer properties and configuring a peripheral is classified elsewhere. This subclass is for data transfer specifying, per se.

34	Transferred data counting:
	This subclass is indented under subclass 33.  Subject matter wherein the amount of the data to be transferred is defined and the amount of data subsequently transferred is computed. (1) Note. As a reminder, the glossary for this class defines a computer as a special instance of a digital data processing system. SEE OR SEARCH THIS CLASS, SUBCLASS: 15+, for digital data processing system or computers detecting or observing operating characteristics or conditions of peripherals.

35	Burst data transfer:
	This subclass is indented under subclass 33.  Subject matter wherein the characteristic is specified as to enable a plurality of data to be transferred in a single transmission.

36	Input/Output access regulation:
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for controlling which of the peripherals may transfer data with which of the digital data processing systems or computers. SEE OR SEARCH THIS CLASS, SUBCLASS: 107+, for access regulation and arbitration within a digital data processing system, 200-244, for generalized locking, polling, access arbitration and interrupt data processing. SEE OR SEARCH CLASS: 709,  Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring,   appropriate subclassesfor transferring data among multiple computer systems. 711,  Electrical Computers and Digital Processing Systems: Memory,   subclasses 200+ for generalized address formation.

37	Access dedication:
	This subclass is indented under subclass 36.  Subject matter further comprising means or steps for permitting certain of the peripherals to exchange data with only certain of the digital data processing system or computers.

38	Path selection:
	This subclass is indented under subclass 36.  Subject matter further comprising means or steps for choosing a route via which the peripheral and digital data processing system or computer will transfer data. SEE OR SEARCH CLASS: 340,  Communications: Electrical,   subclasses 1.1 through 16.1for channel and path selecting in electrical communications, per se.

39	Access request queuing:
	This subclass is indented under subclass 36.  Subject matter further comprising means or steps for storing a request to transfer data from the peripheral, or digital data processing systems or computer so that the request may be serviced later.

40	Access prioritization:
	This subclass is indented under subclass 36.  Subject matter further comprising means or steps for preferring certain of the peripherals, or digital data processing systems or computers over others in servicing requests therefrom to transfer data.

41	Dynamic:
	This subclass is indented under subclass 40.  Subject matter further comprising means or steps for changing preferences given to the peripherals, or digital data processing systems or computers.

42	Group:
	This subclass is indented under subclass 40.  Subject matter further comprising means or steps wherein the preference is based on a class to which the peripherals, or digital data processing systems or computers belong, or on functions the peripherals, or digital data processing system or computers perform.

43	Physical position:
	This subclass is indented under subclass 40.  Subject matter wherein the preference is based on the location of the peripherals, or digital data processing system or computers relative to each other.

44	Prioritized polling:
	This subclass is indented under subclass 40.  Subject matter further comprising means or steps for interrogating the peripherals to determine readiness thereof to transfer data. (1) Note. This subclass requires a determination of a rank of a polled device to carry out a transaction, as opposed to a strictly time-based polling. See the SEE OR SEARCH THIS CLASS, SUBCLASS notes below. SEE OR SEARCH THIS CLASS, SUBCLASS: 46, for polling for access, without prioritized accessing.

45	Time-slot accessing:
	This subclass is indented under subclass 40.  Subject matter further comprising means or steps for cyclically permitting the peripherals, or digital data processing system, or computers to transfer data for fixed periods of time.

46	Input/Output polling:
	This subclass is indented under subclass 36.  Subject matter further comprising means or steps for interrogating the peripherals to determine readiness thereof to transfer data. SEE OR SEARCH THIS CLASS, SUBCLASS: 44, for polling for access combined with prioritized accessing.

47	Polled interrupt:
	This subclass is indented under subclass 46.  Subject matter further comprising means or steps for enabling the computers or digital data processing systems to recognize and respond to interrupt signals from the peripherals by interrogating the peripherals.

48	Input/Output interrupting:
	This subclass is indented under subclass 36.  Subject matter further comprising means or steps for servicing requests for access from the peripheral by suspending processing being performed by the digital data processing system or computer and then granting access to the requesting peripheral. SEE OR SEARCH THIS CLASS, SUBCLASS: 260+, for stopping, halting, or suspending a currently executing processing function within a digital data processing system or computer. SEE OR SEARCH CLASS: 711,  Electrical Computers and Digital Processing Systems: Memory,   subclass 204 for virtual address branch or jump address predicting and subclass 213 for generalized prefetch, look-ahead, jump, or predictive address generating. 712,  Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g. processors),   subclasses 408+ for instruction processing for context switching. 713,  Electrical Computers and Digital Processing Systems: Support,   subclasses 500+ for clock processing, per se. 714,  Error Detection/Correction and Fault Detection/Recovery,   subclass 34 for controlling a processor to be tested or diagnosed by applying an interrupt, halt, or clock signal to the processor, subclass 50 for wherein an ordering of state information related to a succession of data, instructions, etc., is the basis for state analysis. 718,  Electrical Computers and Digital Processing Systems: Virtual Machine Task or Process Management or Task Management/Control,   appropriate subclassesfor task management which generally is triggered by an interrupt event.

49	Masking:
	This subclass is indented under subclass 48.  Subject matter further comprising means or steps for inhibiting the servicing of the access requests. SEE OR SEARCH THIS CLASS, SUBCLASS: 262, for interrupt masking, per se.

50	Vectored:
	This subclass is indented under subclass 48.  Subject matter further comprising means or steps wherein the interrupting peripherals supply, along with the access requests, data identifying locations of routines for servicing the access requests. SEE OR SEARCH THIS CLASS, SUBCLASS: 269, for interrupt processing with handling vector.

51	Accessing via a multiplexer:
	This subclass is indented under subclass 36.  Subject matter further comprising means or steps for employing a concentrator to regulate the access of a plurality of the peripherals, or digital data processing systems or computers.

52	Input/Output data buffering:
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for temporarily storing data being transferred between the peripheral, and digital data processing systems or computer. SEE OR SEARCH CLASS: 326,  Electronic Digital Logic Circuitry,   subclasses 56+ for employing tri-state buffers. 365,  Static Information Storage and Retrieval,   subclass 189.05 for buffering or latching data being read from or written to memories, and subclass 230.08 for buffering or latching address data being employed to access memories. 709,  Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring,   subclass 234 for computer-to-computer data transferring which may include controlling buffer registers. 711,  Electrical Computers and Digital Processing Systems: Memory,   subclasses 118+ for caching under storage accessing and control.

53	Alternately filling or emptying buffers:
	This subclass is indented under subclass 52.  Subject matter further comprising means or steps for temporarily storing the data in plural memories wherein data are stored to and retrieved from at least one of the memories while other data are retrieved from or stored to at least one of the other memories. SEE OR SEARCH CLASS: 711,  Electrical Computers and Digital Processing Systems: Memory,   subclass 5 for addressing multiple memory modules using interleaving techniques, subclass 157 for generalized use of interleaving in memory accessing and control, and subclasses 200+ for generalized addressing techniques.

54	Queue content modification:
	This subclass is indented under subclass 52.  Subject matter further comprising means or steps wherein the data are temporarily stored in a memory and the order in which the data are to be retrieved from the memory is altered.

55	Contents validation:
	This subclass is indented under subclass 52.  Subject matter further comprising means or steps for employing memories to temporarily store the data and for designating whether the memories currently contain data to be transferred therefrom.

56	Buffer space allocation or deallocation:
	This subclass is indented under subclass 52.  Subject matter further comprising means or steps for employing a memory to temporarily store the data and for increasing or decreasing the size of the memory. SEE OR SEARCH CLASS: 711,  Electrical Computers and Digital Processing Systems: Memory,   subclasses 170+ for generalized memory configuring.

57	Fullness indication:
	This subclass is indented under subclass 52.  Subject matter further comprising means or steps for employing a memory to temporarily store the data and for detecting or reporting the amount of data stored in the memory.

58	Input/Output process timing:
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for regulating when functions are performed in order to transfer data between the peripheral and digital data processing system or computer. (1) Note. This subclass is directed to timing considerations for Input/Output processes in communications between a peripheral and digital data processing system or computer. Communication between programs, processes, or tasks (i.e., interprogram communication and interprocess communication) is classified elsewhere. See the SEE OR SEARCH CLASS notes below. SEE OR SEARCH CLASS: 709,  Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring,   appropriate subclassesfor data transferring between plural computers, per se, particularly subclass 248 for synchronizing the operations of plural digital data processing systems and computers. 713,  Electrical Computers and Digital Processing Systems: Support,   subclasses 500+ for clock processing, per se. 718,  Electrical Computers and Digital Processing Systems: Virtual Machine Task or Process Management or Task Management/Control,   appropriate subclassesfor task management which generally is triggered by an interrupt event. 719,  Electrical Computers and Digital Processing Systems: Interprogram Communication or Interprocess Communication (IPC),   appropriate subclassesfor interprogram and interprocess communication.

59	Processing suspension:
	This subclass is indented under subclass 58.  Subject matter further comprising means or steps for temporarily halting the performance of the function (e.g., to wait for data to be transferred from the peripheral).

60	Transfer rate regulation:
	This subclass is indented under subclass 58.  Subject matter further comprising means or steps for setting the speed at which data are exchanged between the peripheral and digital data processing system or computer. SEE OR SEARCH CLASS: 709,  Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring,   subclass 233 for transfer speed regulating in computer-to-computer data transferring.

61	Synchronous data transfer:
	This subclass is indented under subclass 58.  Subject matter further comprising means or steps for exchanging data between the peripheral and digital data processing system or computer accompanied by clock pulses.

62	Peripheral adapting:
	This subclass is indented under subclass 1.  Subject matter further comprising means or steps for making the peripheral compatible with the digital data processing system or computer. (1) Note. Adapting memories or processors to buses is distinguished from peripheral adapting and is classified elsewhere in this class. See the SEE OR SEARCH THIS CLASS, SUBCLASS notes below. SEE OR SEARCH THIS CLASS, SUBCLASS: 100+, for adapting compatible memories or processors to buses, memories to memories, for adapting processors to processors, and for adapting plural buses.

63	Universal:
	This subclass is indented under subclass 62.  Subject matter further comprising means or steps having the capability to interface different types of peripherals to the computer or digital data processing system.

64	Via common units and peripheral-specific units:
	This subclass is indented under subclass 62.  Subject matter further comprising means or steps for employing functional units generic to different types of peripherals and functional units specific to the different types to interface the peripherals and digital data processing systems or computers.

65	Input/Output data modification:
	This subclass is indented under subclass 62.  Subject matter further comprising means or steps for changing a format of data transferred between the peripheral and digital data processing system or computer.

66	Width conversion:
	This subclass is indented under subclass 65.  Subject matter further comprising means or steps for transferring data between a peripheral that processes data of a first size and digital data processing system or computer that process data of a second size, different from the first. (1) Note. Adapting from Input/Output buses to system buses is distinguishable from width converting here and is classified elsewhere in this class. See SEE OR SEARCH THIS CLASS, SUBCLASS below. SEE OR SEARCH THIS CLASS, SUBCLASS: 126+, for various bus architectures and bus width adapting.

67	Keystroke interpretation:
	This subclass is indented under subclass 65.  Subject matter further comprising means or steps for changing a signal that is generated by a keyboard into digital data. SEE OR SEARCH CLASS: 345,  Computer Graphics Processing and Selective Visual Display Systems,   subclasses 156+ for various display peripheral interface input devices including mice and joysticks.

68	Data compression and expansion:
	This subclass is indented under subclass 65.  Subject matter further comprising means or steps for compacting data for more efficient transferring between the peripheral and digital data processing system or computer, or for more efficient storage in peripheral. SEE OR SEARCH CLASS: 380,  Cryptography,   appropriate subclasses for data encryption and decryption, per se. 709,  Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring,   subclass 247 for compression/decompression in computer-to-computer data transferring.

69	Analog-to-digital or digital-to-analog:
	This subclass is indented under subclass 65.  Subject matter further comprising means or steps for changing the format from analog signal to digital data or vice versa. SEE OR SEARCH CLASS: 341,  Coded Data Generation or Conversion,   subclasses 126+ for analog/digital and digital/analog conversion.

70	Digital-to-digital:
	This subclass is indented under subclass 65.  Subject matter further comprising means or steps for changing the format from one type of digital data to another. SEE OR SEARCH CLASS: 341,  Coded Data Generation or Conversion,   subclasses 50+ for digital/digital conversion.

71	Serial-to-parallel or parallel-to-serial:
	This subclass is indented under subclass 65.  Subject matter further comprising means or steps for changing the format from serial to parallel or vice versa.

72	Application-specific peripheral adapting:
	This subclass is indented under subclass 62.  Subject matter further comprising means or steps for making certain types of peripheral compatible with digital data processing system or computer. SEE OR SEARCH CLASS: 345,  Computer Graphics Processing and Selective Visual Display Systems,   subclasses 156+ for various display peripheral interface input devices. 375,  Pulse or Digital Communications,   subclasses 219+ for digital transceivers. 379,  Telephonic Communications,   for two-way transmission of intelligible audio information having arbitrary content over an electrical conductor. 708,  Electrical Computers: Arithmetic Processing and Calculating,   subclasses 131+ for input devices for electric digital calculators, and subclasses 160+ for output devices for electric digital calculators.

73	For user input device:
	This subclass is indented under subclass 72.  Subject matter wherein the peripheral is a user input device other than a keyboard, per se, or a cursor controller, per se. SEE OR SEARCH CLASS: 178,  Telegraphy,   subclasses 18+ for various input devices relying on mechanical pens, electrostatic pens, and the like coacting with a tablet or receiver. 250,  Radiant Energy,   appropriate subclasses, for example subclasses 203.1+ , 215, 229+, and 566+, for a variety of techniques relying on radiant energy that may be used in gathering positional or other information for input to digital data processing system. 345,  Computer Graphics Processing and Selective Visual Display Systems,   subclasses 156+ for various display peripheral interface input devices. 356,  Optics: Measuring and Testing,   appropriate subclasses, for example subclasses 3+ for a variety of techniques that may be used in optically gathering positional or other information for input to digital data processing system. 708,  Electrical Computers: Arithmetic Processing and Calculating,   subclasses 131+ for input devices for electric digital calculators.

74	For data storage device:
	This subclass is indented under subclass 72.  Subject matter wherein the peripheral is a data storage device. SEE OR SEARCH CLASS: 360,  Dynamic Magnetic Information Storage or Retrieval,   appropriate subclasses for record carriers and systems wherein information is stored and retrieved by interaction with a medium and there is relative motion between a medium and a transducer, for example, magnetic disk drive devices and control thereof, per se. 365,  Static Information Storage and Retrieval,   various subclasses for addressable static singular storage elements or plural singular storage elements of the same type. 369,  Dynamic Information Storage Or Retrieval,   appropriate subclasses for processes of and apparatus for the storage or retrieval of arbitrarily variable information which is retained in a storage medium by variation of a physical characteristic thereof. 711,  Electrical Computers and Digital Processing Systems: Memory,   subclasses 100+ for memory accessing and control.

100	INTRASYSTEM CONNECTING (E.G., BUS AND BUS TRANSACTION PROCESSING):
	This subclass is indented under the class definition.  Subject matter comprising means or steps for interconnecting or communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system. (1) Note. This subclass is for processes and apparatus for interfacing only compatible components; components that can communicate data without any format changes or translation are classified in this subclass. Processes and apparatus for interfacing peripherals with incompatible computers or digital data processing systems are classified elsewhere. Processes and apparatus for interfacing other incompatible components of computers or digital data processing systems are classified elsewhere. See the SEE OR SEARCH CLASS notes below. (2) Note. This subclass requires more than nominal recitation of intrasystem connections and communication. For example, processing architecture art areas, including virtual processors, MIMD, vector and array processors, and single-chip microprocessors which only nominally include recitation of intrasystem connections and communication are classified elsewhere. See the SEE OR SEARCH CLASS notes below. SEE OR SEARCH THIS CLASS, SUBCLASS: 62+, for making peripherals compatible with computers or digital data processing systems. SEE OR SEARCH CLASS: 326,  Electronic Digital Logic Circuitry,   subclass 30 for bus or line terminating circuitry, and subclasses 62+ for generic digital logic gate level interface circuitry. 340,  Communications: Electrical,   subclasses 1.1 through 16.1for controlling one or more devices to obtain a plurality of results by transmission of a designated one of plural distinctive control signals over a smaller number of communication lines or channels, particularly subclasses 2.1-2.8 for path selection, subclass 2.81 for tree or cascade selective communication, subclasses 3.1-3.9 for communication systems where status of a controlled device is communicated, subclasses 4.2 and 4.21 for synchronizing selective communication systems, subclasses 9.1-9.17 for addressing in selective communication systems, and subclasses 12.1-12.55 for pulse responsive actuation in selective communication systems. 370,  Multiplex Communications,   appropriate subclasses for the simultaneous transmission of two or more signals over a common medium. 703,  Data Processing: Structural Design, Modeling, Simulation, and Emulation,   subclasses 23 through 28for general purpose compatibility, simulation, or emulation of system components for interfacing between incompatible components of computers or digital data processing systems. 712,  Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g. processors),   appropriate subclasses for processing architecture art areas, including virtual processors, MIMD, vector and array processors, and single-chip microprocessors which nominally include recitation of intrasystem connections and communication.

104	System configuring:
	This subclass is indented under subclass 100.  Subject matter including means or steps for utilizing a hardware structure for providing to a processor arrangement data of the digital data processing system including a characteristic of the digital data processing system"s component. (1) Note. Configuration at booting via software is classified elsewhere. See the SEE OR SEARCH CLASS notes below. (2) Note. Assigning operating characteristics to peripherals is classified elsewhere in this class. See the SEE OR SEARCH THIS CLASS, SUBCLASS notes below. SEE OR SEARCH THIS CLASS, SUBCLASS: 8, for assigning operating characteristics to peripherals. SEE OR SEARCH CLASS: 713,  Electrical Computers and Digital Processing Systems: Support,   subclasses 1 , 2, and 100 for digital data processing system initialization and configuration at boot-time.

105	Protocol:
	This subclass is indented under subclass 100.  Subject matter including means or steps for providing an exchange of information in accordance with a set of rules or standards designed to enable digital data processing system components to connect with each other. SEE OR SEARCH THIS CLASS, SUBCLASS: 11, for Input/Output protocol selecting for data transfer between a computer and peripheral(s). SEE OR SEARCH CLASS: 340,  Communications: Electrical,   various subclasses for residual electrical communication systems. 370,  Multiplex Communications,   various subclasses for generic multiplexing and demultiplexing systems. 375,  Pulse or Digital Communications,   various subclasses for generic pulse or digital communication systems. 709,  Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring,   subclasses 230+ for computer-to-computer data transfer protocol implementing.

106	Using transmitter and receiver:
	This subclass is indented under subclass 105.  Subject matter including means or steps using a transmitter and receiver for exchanging the information between the digital data processing system components. SEE OR SEARCH CLASS: 375,  Pulse or Digital Communications,   subclasses 219+ for digital transceivers.

107	Bus access regulation:
	This subclass is indented under subclass 100.  Subject matter including means or steps for providing control signals and commands to digital data processing system components connected to the bus in order to maintain information-handling or bus activities. SEE OR SEARCH THIS CLASS, SUBCLASS: 28, for DMA with access regulating. 36+, for access regulating in the transferring of data from one or more peripherals to one or more computers for the latter to process, store, or further transfer or for transferring data from the computers to the peripherals (i.e., Input/Output processing access regulating). 200-244, for generalized locking, polling, access arbitrating, and interrupt processing. SEE OR SEARCH CLASS: 370,  Multiplex Communications,   appropriate subclasses for TDM, FDM, etc., subclasses 352+ and 389+ for packetized multiplex communications, subclasses 438+ for access control by a separate control line or bus, and 445+ for bus contention including carrier sense. 709,  Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring,   subclass 225 for computer network access regulating in multicomputer data transferring. 711,  Electrical Computers and Digital Processing Systems: Memory,   subclass 150 for regulating simultaneous access to shared memory. 713,  Electrical Computers and Digital Processing Systems: Support,   subclass 2 for process scheduling. 718,  Electrical Computers and Digital Processing Systems: Virtual Machine Task or Process Management or Task Management/Control,   appropriate subclassesfor task management and control related to process or job execution.

108	Bus locking:
	This subclass is indented under subclass 107.  Subject matter including means or steps for preventing access by a digital data processing system component to a shared interconnecting medium while another digital data processing system component has temporary exclusive control of the interconnecting medium. SEE OR SEARCH CLASS: 455,  Telecommunications,   subclass 26.1 for subject matter which blocks access to a signal source or otherwise limits usage of modulated carrier equipment.

109	Bus polling:
	This subclass is indented under subclass 107.  Subject matter including means or steps for bus access regulating by determining the status of each digital data processing system component in a digital data processing system by another processing digital data processing system component which accesses each of the digital data processing system components one at a time. (1) Note. Classification herein allows appropriate action such as granting access according to a status determination. (2) Note.Subject matter directed to the interrogation of peripherals is classified elsewhere in this class. See the SEE OR SEARCH THIS CLASS, SUBCLASS notes below. (3) Note. Generalized access polling is classified elsewhere in this class. See the SEE OR SEARCH THIS CLASS, SUBCLASS notes below. SEE OR SEARCH THIS CLASS, SUBCLASS: 44+, for subject matter directed to polled interrogation of peripherals. 220, for generalized access polling under the class definition. SEE OR SEARCH CLASS: 370,  Multiplex Communications,   subclasses 451+ for bus polling.

110	Bus master/slave controlling:
	This subclass is indented under subclass 107.  Subject matter wherein a digital data processing system component is provided with control over other digital data processing system components connected to the bus. SEE OR SEARCH CLASS: 700,  Data Processing: Generic Control Systems or Specific Applications,   subclasses 2 through 7for the use of plural processors and a master/slave arrangement in a digital generic control system application. 709,  Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring,   subclasses 208+ for multicomputer master/slave arrangements.

111	Rotational prioritizing (i.e., round robin):
	This subclass is indented under subclass 107.  Subject matter including means or steps for granting bus access to all contending digital data processing system components one at a time in a predetermined order before any one digital data processing system components may again obtain the bus.

112	Bus request queuing:
	This subclass is indented under subclass 107.  Subject matter including means or steps for storing requests for access to the bus in the order in which they are received. SEE OR SEARCH THIS CLASS, SUBCLASS: 54, for I/O data buffering queue content modifying.

113	Centralized bus arbitration:
	This subclass is indented under subclass 107.  Subject matter including means or steps for determining which of plural digital data processing system components contending for access to a shared bus shall be granted access at any one time, wherein the determination is performed by a single digital data processing system component common to the digital data processing system components. SEE OR SEARCH THIS CLASS, SUBCLASS: 36+, for access regulating in the transferring of data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, or further transfer or for transferring data from the computers or digital data processing systems to the peripherals (i.e., Input/Output processing access regulating). 119, for decentralized bus arbitration. 200-269, for generalized locking, polling, access arbitrating, and interrupt processing.

114	Static bus prioritization:
	This subclass is indented under subclass 113.  Subject matter including means or steps for granting the contending plural digital data processing system components access to the bus in accordance with a fixed ranking assigned to each digital data processing system component. SEE OR SEARCH THIS CLASS, SUBCLASS: 121, for decentralized static bus prioritization.

115	Physical position bus prioritization:
	This subclass is indented under subclass 114.  Subject matter including means or steps for granting the contending digital data processing system components access to the shared bus based on their physical location on the bus. SEE OR SEARCH THIS CLASS, SUBCLASS: 122, for decentralized physical position bus prioritization.

116	Dynamic bus prioritization:
	This subclass is indented under subclass 113.  Subject matter including means or steps for changing the ranking of the contending digital data processing system components. SEE OR SEARCH THIS CLASS, SUBCLASS: 123, for decentralized dynamic bus prioritization.

117	Time-slotted bus accessing:
	This subclass is indented under subclass 113.  Subject matter including means or steps for granting the contending digital data processing system components use of the shared bus for a predetermined time period. SEE OR SEARCH THIS CLASS, SUBCLASS: 124, for decentralized time-slotted bus accessing.

118	Delay reduction:
	This subclass is indented under subclass 113.  Subject matter including means or steps for decreasing the arbitration time among the contending digital data processing system components on the bus. SEE OR SEARCH THIS CLASS, SUBCLASS: 125, for decentralized bus delay reduction.

119	Decentralized bus arbitration:
	This subclass is indented under subclass 107.  Subject matter including means or steps for determining which of plural digital data processing system components contending for access to a shared bus shall be granted access at any one time, wherein the determination is performed by circuitry located in more than one of the contending digital data processing system components. SEE OR SEARCH THIS CLASS, SUBCLASS: 36+, for access regulating in the transferring of data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, or further transfer or for transferring data from the computers or digital data processing systems to the peripherals (i.e., Input/Output processing access regulating). 113, for a centralized bus arbitration. 200-269, for generalized locking, polling, access arbitrating, and interrupt processing.

120	Hierarchical or multilevel accessing:
	This subclass is indented under subclass 119.  Subject matter including means or steps for performing more than one level of bus arbitration in order to grant access to one of the contending digital data processing system components. SEE OR SEARCH THIS CLASS, SUBCLASS: 243, for generalized multilevel access arbitrating.

121	Static bus prioritization:
	This subclass is indented under subclass 119.  Subject matter including means or steps for granting the contending plural digital data processing system components access to the bus in accordance with a fixed ranking assigned to each digital data processing system component. SEE OR SEARCH THIS CLASS, SUBCLASS: 114, for centralized static bus prioritization.

122	Physical position bus prioritization:
	This subclass is indented under subclass 121.  Subject matter including means or steps for granting the contending digital data processing system components access to the shared bus based on their physical location on the bus. SEE OR SEARCH THIS CLASS, SUBCLASS: 115, for centralized physical position bus prioritization.

123	Dynamic bus prioritization:
	This subclass is indented under subclass 119.  Subject matter including means or steps for changing the ranking of the contending digital data processing system components. SEE OR SEARCH THIS CLASS, SUBCLASS: 116, for centralized dynamic bus prioritization.

124	Time-slotted bus accessing:
	This subclass is indented under subclass 119.  Subject matter including means or steps for granting the contending digital data processing system components use of the shared bus for a predetermined time period. SEE OR SEARCH THIS CLASS, SUBCLASS: 117, for centralized time-slotted bus accessing. SEE OR SEARCH CLASS: 370,  Multiplex Communications,   various subclasses for generic multiplexing and demultiplexing systems.

125	Delay reduction:
	This subclass is indented under subclass 119.  Subject matter including means or steps for decreasing the arbitration time among the contending digital data processing system components on the bus. SEE OR SEARCH THIS CLASS, SUBCLASS: 118, for centralized delay reduction.

200	ACCESS LOCKING:
	This subclass is indented under the class definition.  Subject matter comprising means or steps for preventing access to a shared resource of a computer or digital data processing system. (1) Note. Processes and apparatus for locking access for general utility are classified herein. Processes and apparatus for locking access to buses are classified elsewhere. See the SEE OR SEARCH THIS CLASS, SUBCLASS notes below. Processes and apparatus for locking access to memories are classified elsewhere. See the SEE OR SEARCH CLASS notes below. (2) Note. Processes and apparatus for regulating simultaneous access to a computer network are classified elsewhere. See the SEE OR SEARCH CLASS notes below. (3) Note. Processes and apparatus for furthering the security of computers and digital data processing systems, even if the processes and apparatus involve access locking, are classified in this class elsewhere. See the SEE OR SEARCH CLASS notes below. SEE OR SEARCH THIS CLASS, SUBCLASS: 108, for bus locking. SEE OR SEARCH CLASS: 340,  Communications: Electrical,   subclasses 5.1 through 5.92for security (e.g., authorization) in selective communication systems, particularly, subclasses 5.22-5.25 for varying authorization control using programmable code. 380,  Cryptography,   subclass 4 for stored digital data access or copy prevention in combination with data encryption; e.g., software program protection or computer virus detection in combination with data encryption. 455,  Telecommunications,   subclass 26.1 for subject matter which blocks access to a signal source or otherwise limits usage of modulated carrier equipment. 711,  Electrical Computers and Digital Processing Systems: Memory,   subclasses 163+ for limiting access to memories. 714,  Error Detection/Correction and Fault Detection/Recovery,   subclass 763 for memory access block coding, and subclass 805 for storage accessing error/fault detection techniques. 726,  Information Security,   subclasses 1 through 36for information security in computers or digital processing system.

220	ACCESS POLLING:
	This subclass is indented under the class definition.  Subject matter comprising means or steps for granting access to a shared resource of a computer of digital data processing system by one of a plurality of components of the computer or digital data processing system by interrogating each of the components in a predetermined order. (1) Note. Processes and apparatus for access polling of general utility are classified herein. Processes and apparatus for access polling of peripherals and for access polling of a bus are classified elsewhere in this class. See the SEE OR SEARCH THIS CLASS, SUBCLASS notes below. (2) Note. Processes and apparatus for regulating simultaneous access to a computer network are classified elsewhere. See the SEE OR SEARCH CLASS notes below. (3) Note. Processes and apparatus for regulating simultaneous access to shared memory are classified elsewhere. See the SEE OR SEARCH CLASS notes below. SEE OR SEARCH THIS CLASS, SUBCLASS: 28, for direct memory access (DMA) with access regulating 36+, for digital data processing system input/output access regulating. 46-47, for access polling of peripherals. 107+, for bus access regulating in a digital data processing system. 109, for access polling of a bus. SEE OR SEARCH CLASS: 370,  Multiplex Communications,   subclasses 445+ for bus contention including carrier sense. 711,  Electrical Computers and Digital Processing Systems: Memory,   subclass 150 for regulating simultaneous access to shared memory.

240	ACCESS ARBITRATING:
	This subclass is indented under the class definition.  Subject matter comprising means or steps for determining which of a plurality of components of a computer system or digital data processing system contending for access to a shared resource shall be granted access at any one time based upon a predetermined criteria. (1) Note. For classification herein it is adequate that the grant is determined. The access grant is not required for classification herein. (2) Note. Processes and apparatus for regulating simultaneous access to a computer network are classified elsewhere. See the SEE OR SEARCH CLASS notes below. SEE OR SEARCH THIS CLASS, SUBCLASS: 28, for direct memory access (DMA) with access regulating 36+, for digital data processing system input/output access regulating. 107+, for bus access regulating in a computer or digital data processing system. SEE OR SEARCH CLASS: 370,  Multiplex Communications,   subclasses 445+ for bus contention including carrier sense. 709,  Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring,   subclass 225 for regulating simultaneous access to a computer network. 711,  Electrical Computers and Digital Processing Systems: Memory,   subclass 150 for regulating simultaneous access to shared memory.

241	Centralized arbitrating:
	This subclass is indented under subclass 240.  Subject matter further comprising means or steps for performing the arbitration for the contending digital data processing system components by a single processor. SEE OR SEARCH THIS CLASS, SUBCLASS: 113+, for centralized bus access regulating in a digital data processing system.

242	Decentralized arbitrating:
	This subclass is indented under subclass 240.  Subject matter further comprising means or steps for performing the arbitration for the contending digital data processing system components by circuitry resident in each of the contending digital data processing system components. SEE OR SEARCH THIS CLASS, SUBCLASS: 119+, for decentralized bus access regulating in a digital data processing system.

243	Hierarchical or multilevel arbitrating:
	This subclass is indented under subclass 240.  Subject matter further comprising means or steps for performing more than one level of arbitration. SEE OR SEARCH THIS CLASS, SUBCLASS: 120, for decentralized multilevel bus accessing. SEE OR SEARCH CLASS: 711,  Electrical Computers and Digital Processing Systems: Memory,   subclasses 117+ for hierarchical memory accessing and control.

244	Access prioritizing:
	This subclass is indented under subclass 240.  Subject matter further comprising means or steps for granting the access in accordance with a predetermined ranking.

260	INTERRUPT PROCESSING:
	This subclass is indented under the class definition.  Subject matter comprising means or steps for stopping, halting, or suspending a current processing function within a computer or digital data processing system. SEE OR SEARCH THIS CLASS, SUBCLASS: 48+, for Input/Output device interrupt data processing. SEE OR SEARCH CLASS: 711,  Electrical Computers and Digital Processing Systems: Memory,   subclasses 204+ for virtual address branch or jump address predicting and subclass 213 for generalized prefetch, look-ahead, jump, or predictive address generating. 712,  Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g. processors),   appropriate subclasses for instruction data processing, per se. 713,  Electrical Computers and Digital Processing Systems: Support,   appropriate subclasses for processes and apparatus used for the synchronizing the clocking or timing operations of a processor. 714,  Error Detection/Correction and Fault Detection/Recovery,   subclass 34 for controlling a processor to be tested or diagnosed by applying an interrupt, halt, or clock signal to the processor and subclass 50 wherein an ordering of state information related to a succession of data, instructions etc., is the basis for state analysis. 718,  Electrical Computers and Digital Processing Systems: Virtual Machine Task or Process Management or Task Management/Control,   appropriate subclassesfor data processing task management.

261	Multimode interrupt processing:
	This subclass is indented under subclass 260.  Subject matter wherein the digital data processing system or computer has multiple modes of operation and further comprising means or steps for processing the interrupt differently depending on a mode of operation of the digital data processing system or computer.

262	Interrupt inhibiting or masking:
	This subclass is indented under subclass 260.  Subject matter further comprising means or steps for ignoring or delaying the interrupt.

263	Interrupt queuing:
	This subclass is indented under subclass 260.  Subject matter further comprising means or steps for storing interrupt signals for later execution.

264	Interrupt prioritizing:
	This subclass is indented under subclass 260.  Subject matter further comprising means or steps for processing plural interrupts in accordance with a predetermined ranking.

265	Variable:
	This subclass is indented under subclass 264.  Subject matter further comprising means or steps for changing a priority level of at least one interrupt in dependence on system conditions.

266	Programmable interrupt processing:
	This subclass is indented under subclass 260.  Subject matter further comprising means or steps for processing the interrupt under the influence of a user changeable or replaceable stored program.

267	Processor status:
	This subclass is indented under subclass 260.  Subject matter further comprising means or steps for processing the interrupt in accordance with the current condition of the digital data processing system, processor, or computer.

268	Source or destination identifier:
	This subclass is indented under subclass 260.  Subject matter wherein the interrupt signal includes data identifying the source or destination of the interrupt.

269	Handling vector:
	This subclass is indented under subclass 260.  Subject matter wherein the interrupt includes branch address data or a peripheral unit identifier data identifying the location of an interrupt handling routine. SEE OR SEARCH CLASS: 718,  Electrical Computers and Digital Processing Systems: Virtual Machine Task or Process Management or Task Management/Control,   appropriate subclassesfor task management and control. 719,  Electrical Computers and Digital Processing Systems: Interprogram Communication or Interprocess Communication (IPC),   appropriate subclassesfor interprogram communication.

300	Bus expansion or extension:
	This subclass is indented under subclass 100.  Subject matter including means or steps for electrically connecting additional circuit boards to the interconnection medium. (1) Note. This subclass will accept computer docking stations for docking portable computers.

301	Card insertion:
	This subclass is indented under subclass 300.  Subject matter wherein an additional circuit board is capable of being plugged into or removed from a motherboard, backplane, or bus. SEE OR SEARCH CLASS: 361,  Electricity: Electrical Systems and Devices,   subclass 1 for safety and protection of systems and devices.

302	Hot insertion:
	This subclass is indented under subclass 301.  Subject matter including means or steps for allowing plug-in or removal of the additional circuit board into or out of a powered motherboard or backplane.

303	Docking station:
	This subclass is indented under subclass 300.  Subject matter wherein a portable computer is electrically connected to the interconnection medium. SEE OR SEARCH CLASS: 361,  Electricity: Electrical Systems and Devices,   subclasses 679.02 through 679.61for housing or mounting assemblies for computers, digital data processing systems, calculators or components thereof.

304	Hot docking:
	This subclass is indented under subclass 303.  Subject matter including means or steps for allowing plug-in or removal of the portable computer to the interconnection medium wherein at least one of the portable computer or interconnection medium is powered.

305	Bus interface architecture:
	This subclass is indented under subclass 100.  Subject matter including means or steps for providing an interconnection structure for data transfer between digital data processing system components and a bus.

306	Bus bridge:
	This subclass is indented under subclass 305.  Subject matter wherein the interface architecture couples two or more buses to one another.

307	Variable or multiple bus width:
	This subclass is indented under subclass 306.  Subject matter wherein the coupled buses have different bit sizes. SEE OR SEARCH CLASS: 711,  Electrical Computer and Digital Processing Systems: Memory,   subclass 201 for boundary alignment. 712,  Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g. processors),   204 for instruction aligning

308	Direct memory accessing (e.g., DMA):
	This subclass is indented under subclass 306.  Subject matter further comprising means or steps for transferring data between peripherals and memories under control of the bus bridge with little or no intervention from a main processor. SEE OR SEARCH THIS CLASS, SUBCLASS: 22+, for Direct Memory Accessing (DMA)as an I/O operation. SEE OR SEARCH CLASS: 709,  Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring,   subclass 212, computer-to-computer direct memory accessing. 711,  Electrical Computer and Digital Processing Systems: Memory,   subclasses 100 through 173,storage accessing and control. 714,  Error Detection/Correction and Fault Detection/Recovery,   appropriate subclasses for detecting or correcting errors in generic electrical pulse or pulse coded data and for detecting and recovering from faults of computers, particularly subclass 5.11 for access processor affected; digital data processing systems, and logic level based systems, particularly subclass 702 for memory access (e.g., address permutation, etc.); subclasses 710-711 for replacement with spare memory components or portion thereof; subclasses 718-723 for memory testing; and subclasses 763-773 for memory access with error correction, error pointer, or error checking.

309	Arbitration:
	This subclass is indented under subclass 306.  Subject matter wherein the bus bridge includes means or steps for determining which of plural digital data processing system components contending for access to a coupled bus at any one time.

310	Buffer or que control:
	This subclass is indented under subclass 306.  Subject matter including specific means or steps for control of temporary storage of data being transferred between coupled buses

311	Intelligent bridge:
	This subclass is indented under subclass 306.  Subject matter wherein the bridge includes advanced arithmetic and logic functions for controlling bridge operations.

312	Multiple bridges:
	This subclass is indented under subclass 306.  Subject matter including two or more bridges coupling three or more buses.

313	Peripheral bus coupling (e.g., PCI, USB, ISA, and etc.):
	This subclass is indented under subclass 306.  Subject matter wherein one of the coupled buses is an input/output bus (e.g., Peripheral Component Interconnect, Universal Serial Bus, Industry Standard Architecture, and etc.).

314	Common protocol (e.g., PCI to PCI):
	This subclass is indented under subclass 306.  Subject matter wherein the coupled buses operate according to the same signaling requirements (e.g., Peripheral Component Interconnect to Peripheral Component Interconnect).

315	Different protocol (e.g., PCI to ISA):
	This subclass is indented under subclass 306.  Subject matter wherein the coupled buses operate according to signaling requirements which are not the same (e.g., Peripheral Component Interconnect to Industry Standard Architecture).

316	Path selecting switch:
	This subclass is indented under subclass 305.  Subject matter including means or steps for establishing a temporary connection or link between two digital data processing system components by an intermediary station that serves to provide the connection. (1) Note. The subject matter here in accordance with its parent subclass and its class requires connecting and reconnecting of links within a single digital data processing system or computer which distinguishes it from electrical communications switching, telephone switching systems, and computer network switching. See the see or search class notes below. SEE OR SEARCH CLASS: 340,  Communications: Electrical,   subclasses 1.1 through 16.1for subject matter including means or steps for electrical communications switching. 370,  Multiplex Communications,   for the simultaneous transmission of two or more signals over a common medium, particularly 229-240 for data flow congestion prevention and control, subclasses 254 through 258for network configuration determination, subclasses 351-430 for pathfinding or routing which includes circuit switching or packet switching, and subclasses 465-473 for adaptive communication which includes processing or converting of communication protocols. 379,  Telephonic Communications,   for subject matter including means or steps for telephone switching systems. 709,  Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring,   appropriate subclassesfor means or steps for computer network switching. wherein the graphics display memory includes plurality of color planes for storing color image information which may be accessed independently.

317	Crossbar:
	This subclass is indented under subclass 316.  Subject matter wherein the intermediary station or stations are comprised of a matrix of switch points.

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